| Distance: | Job alert | Jobs 71 - 80 of 1062 |
Firmware Engineer with Security Clearance
Equiliem
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Lexington, MA, 02420
... Hybrid - onsite 3-4 days/week Clearance - must be able to clear to the Secret or TS level This candidate will perform FPGA development and will synthesize RTL code written in VHDL or Verilog into a working FPGA. Additionally, this candidate is also ... - Jul 16
SoC Power Analysis and Optimization Engineer
Apple
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San Diego, CA
$139,500-$258,100/year
... Familiarity with ASIC power analysis and optimization Familiarity with SOC design flow and methodology Familiarity with Verilog and System Verilog. Familiarity computer architecture, logic and circuits design Familiarity signal processing is a plus ... - Jul 06
IC/Digital Mixed Signal Verification Engineer with Security Clearance
Associates Systems LLC
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Linthicum Heights, MD, 21090
... Required Education: Bachelor's degree in a technical area (BSEE or other Engineering discipline preferred) with 5 years of relevant experience (3 years with technical MS) - Experience in HDL (VHDL/Verilog) and HVL (SystemVerilog) OR Bachelor's ... - Jul 16
Hardware Logic Designer
INFUSE
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Kharkiv, Kharkiv Oblast, Ukraine
... 4–5 years of hands-on experience in logic design, microarchitecture, and RTL coding in Verilog. Proven experience with VCS, Verdi, and Spyglass—or similar tools. Experience with FPGA design and implementation, including synthesis, place, and route. ... - Jul 01
Senior UVM Digital Verification Engineer
Distinctive Talent Partners, LLC
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Cambridge, MA
160000USD - 190000USD per year
... to debug simulation failures Implement VIPs for protocols like DDR3/DDR4, AMBA AXI Perform formal analysis and use System Verilog assertions (SVA) Script automation flows using Python, Bash, or Perl Review code and mentor junior team members ... - Jul 18
ASIC Design Engineer
Meta
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Bengaluru, Karnataka, India
... RTL development using Verilog, System Verilog and HLS. Lint, CDC, Synthesis, & Power Optimization. Soft and hard IP identification, selection and integration. Collaboration with verification and emulation teams in test plan development and debug. ... - Jul 10
GPU Formal Design Verification Engineer
Apple
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Austin, TX
... Experience with HDLs such as Verilog/System Verilog and temporal logic assertion-based languages such as SVA. Experience in formal verification and analysis of pipelined micro-architectures, MMUs, and cache coherency control mechanisms. Experience ... - Jul 03
Staff or Senior Staff FPGA Design Engineer
GreenWave Radios™
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Irvine, CA
... systems, wireless protocols, power management, signal processing and standard digital interfaces RTL design knowledge (Verilog/VHDL) and SystemVerilog Knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers) ... - Jul 19
SoC DFT Engineer
Apple
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Austin, TX
... Knowledge of Verilog and/or VHDL, and experience with simulators and waveform debugging tools. Knowledge of industry standards for DFT and design tools. Proven Understanding of design verification (DV) methodologies for validating DFT implementation ... - Jul 10
ASIC Engineer, Design
META
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Rollingwood, TX, 78716
... Degree must be completed prior to joining Meta 2+ years of experience in micro-architecture and RTL development for complex control and data path IPs OR Experience in SoC Micro-architecture, Design and Integration RTL development using Verilog, ... - Jul 16