| Distance: | Job alert | Jobs 81 - 90 of 3180 |
PHY Design Verification Engineer
Apple Inc.
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California
... communication systems engineers to develop reusable testbench and verification environment deploying the latest methodology with metric-driven verification, ensuring the highest design quality.Advanced knowledge of Verilog, SystemVerilog, and UVM. ... - Oct 26
Analog IC Design Engineer
Apple Inc.
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Cupertino, CA, 95014
... techniques in presence of device mismatch Experience in C / Matlab / Verilog modeling Strong device physics knowledge as it applies to analog IC designs Proven working experience in using spectrum analyzers, oscilloscopes, signal generators, etc. ... - Nov 01
Wireless Design Verification Engineer
Apple Inc.
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California
... communication systems engineers to develop reusable test bench and verification environment deploying the latest methodology with metric-driven verification, ensuring the highest design quality.Advanced knowledge of Verilog, SystemVerilog, and UVM. ... - Oct 26
PHY Design Verification Engineer
Apple Inc.
–
California
... Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion. Excellent knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage. Experience of ... - Oct 25
Wireless Design Verification Engineer
Apple Inc.
–
California
... Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion. Knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage. Verification experience ... - Oct 25
Test Engineer
Teledyne
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Goleta, CA, 93117
... + Desired familiarity with Verilog, Xilinx ISE, Quartus FPGA development and maintenance. + Strong computer skills, including Microsoft Office (Word, Excel) **_Applicants must be either a U.S. citizen, U.S. national, legal permanent resident, asylee ... - Oct 26
Wireless Design Verification Engineer
Apple Inc.
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California
... Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion. Knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage. Verification experience ... - Oct 26
Design Verification Engineer
Apple Inc.
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San Diego, CA, 92140
... We also require additional responsibilities such as running and triaging regressions, tracking bugs, and analyzing coverage to achieve top results.Knowledge of computer architecture and digital design fundamentals Knowledge of Verilog or ... - Oct 22
PHY Design Verification Engineer
Apple Inc.
–
California
... Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion. Excellent knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage. Experience of ... - Oct 25
PHY Design Verification Engineer
Apple Inc.
–
California
... Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion. Excellent knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage. Experience of ... - Oct 26