| Distance: | Job alert | Jobs 21 - 30 of 1073 |
Sr. FPGA Engineer (Contract-Perm)
A2e Technologies
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Tujunga, CA, 91329
... Start Date: ASAP Requirements 10+ Years experience: FPGA/Modem Design Ultrascale+ & Versal Strong Design skills in VHDL & Verilog Extensive experience w/Bring-up Verilog and Python based Simulations Solid background in networking using ETH/IP/UDP ... - Jul 15
(Staff/Sr. Staff) NPU Design Engineer
Omnivision Technologies, Inc.
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Singapore, Central Singapore Community Development
... Microarchitecture design and RTL coding using Verilog / System Verilog HDL for various sub-blocks of the NPU. Understanding the mathematics of different convolution operators including different arithmetic formats (fixed point and floating point) ... - Jul 04
Principal / Lead, FPGA & SoC Architecture (Wi-Fi Baseband)
Edgewater Wireless Systems Inc.
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Ottawa, ON, Canada
... ● Minimum of 10 years of experience in digital hardware design, with significant experience in FPGA development and prototyping for complex systems (using Verilog/VHDL and SystemVerilog). ● Proven experience architecting and implementing complex ... - Jul 11
ISP RTL Design Engineer
Omnivision Technologies, Inc.
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Singapore, Central Singapore Community Development
Responsibilities Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Verify Logic at ISP level and Digital System level Optimize Design for less gate count and low power consumption ... - Jul 04
(Sr.) ISP RTL Design Manager
Omnivision Technologies, Inc.
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Singapore, Central Singapore Community Development
Responsibilities: Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Define ISP HW Architecture based on product features and performance requirements, also with gate count and power ... - Jul 04
Staff ASIC Verification Engineer
Infinera
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Ottawa, ON, Canada
... Title: Staff ASIC Verification Engineer Location: Ottawa, Canada Responsibilities · Contribute significantly to verification infrastructure development · Development of System Verilog/UVM-based protocol/traffic generators/checkers, development of ... - Jun 27
CAD Engineer - RTL Construction
Apple
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Beaverton, OR
... Minimum requirement of Bachelors Degree +10 years of relevant industry experience Experience in programming languages such as Perl or Python Experience in Verilog/System Verilog Demonstrated experience driving large-scale software system development ... - Jul 04
FPGA/ASIC Design Engineer
TeamGlobal
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Camden, NJ
... * Additionally, S/He will be responsible for writing/debugging tests/sequences for End-to-End simulation on UVM framework, with System Verilog Assertions, and also writing/debugging C++ based SW driven validation on SOC evaluation boards (Xilinx ... - Jul 14
CAD Engineer - RTL Construction
Apple
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Cupertino, CA
$147,400-$272,100/year
... Minimum requirement of Bachelors Degree +3 years of relevant industry experience Experience in programming languages such as Perl or Python Experience in Verilog/System Verilog Demonstrated experience driving large-scale software system development ... - Jul 06
(Sr./Staff) SoC Design Engineer
Omnivision Technologies, Inc.
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Singapore, Central Singapore Community Development
... You would be responsible for the successful implementation of the designs in Verilog/SystemVerilog coding, metrics measurement to meet key objectives & results, and follow-through in comprehensive verifications to successful silicon. Requirements: ... - Jul 04