| Distance: | Job alert | Jobs 31 - 40 of 1035 |
Staff ASIC Verification Engineer
Infinera
–
Ottawa, ON, Canada
... Title: Staff ASIC Verification Engineer Location: Ottawa, Canada Responsibilities · Contribute significantly to verification infrastructure development · Development of System Verilog/UVM-based protocol/traffic generators/checkers, development of ... - Jun 27
FPGA/ASIC Design Engineer
TeamGlobal
–
Camden, NJ
... * Additionally, S/He will be responsible for writing/debugging tests/sequences for End-to-End simulation on UVM framework, with System Verilog Assertions, and also writing/debugging C++ based SW driven validation on SOC evaluation boards (Xilinx ... - Jul 14
ASIC Design Engineer - Pixel IP
Apple
–
Cupertino, CA
$147,400-$272,100/year
... Experience in SoC front-end ASIC RTL digital logic design with using Verilog or System Verilog. Experience working cross-functionally with architecture, design, and verification teams to specify, design, and debug designs. Good collaboration skills ... - Jul 06
CAD Engineer - RTL Construction
Apple
–
Cupertino, CA
$147,400-$272,100/year
... Minimum requirement of Bachelors Degree +3 years of relevant industry experience Experience in programming languages such as Perl or Python Experience in Verilog/System Verilog Demonstrated experience driving large-scale software system development ... - Jul 06
SoC Design Engineer
Steinman Recruiting Associates
–
Santa Clara, CA, 95050
$180000 - $220000 / yr
... System Verilog. Highly Desirable: PhD/MS Chiplet technologies (2, 3, 5 nm). Work experience in design services. 2-3 of the following: CPU (preferably, ARM and/or RISC-V), or GPU, or DSP; SoC Memory hierarchy; NoC -Fabric; low-power design and ... - Jul 09
Ethernet ASIC Design Engineer
Cornelis Networks
–
Wayne, PA, 19087
... Implement Ethernet protocols such as Priority Flow Control, TCP, UDP, RoCEv2, VLAN, ECMP, DCQCN, ECN, and Security in Transmit and Receive pipelines using Verilog/System Verilog. Collaborate with verification engineers to create block- and system ... - Jul 20
Mixed-Signal IC Design Engineer
Apple
–
Cupertino, CA
$181,100-$318,400/year
... test plans, optimize production testing, and debug sources of low-DPPM parametric yield loss Experience in C / MATLAB / Verilog modeling Proficiency in Python programming Experience with AI/ML, especially in applying tools and technique to any/all ... - Jul 06
VLSI Design Engineer
WhiteLotus Talent Partners Pvt Ltd
–
Texas
... Required Skills: Proficiency in RTL coding with Verilog/SystemVerilog. Experience with IP/SOC integration and standard protocols (AXI, PCIe, DDR, USB). Strong understanding of SoC design flows and toolchains (e.g., Synopsys, Cadence). Good command ... - Jul 22
Staff Firmware/Embedded Systems Engineer
Empower Semiconductor
–
San Jose, CA
... Familiarity with Verilog and System Verilog models would be an advantage Experience with software configuration management tools, defect tracking tools, and peer review processes. Good communication skills in verbal and written form Strong sense of ... - Jul 15
Senior Staff ASIC Design Engineer, Neural Processor
Syntiant
–
Redwood City, CA
... RTL implementation of Digital Signal Processing algorithms, using Verilog or System Verilog. Implementation of test benches and digital verification methods. Experience in PPA (Power/Performance/Area) optimizations. Programming/scripting languages ... - Jul 21