| Resume alert | Resumes 1 - 10 of 123 |
Sql Server Software Development
Plano, TX
... Programming Languages: T-SQL,Oracle SQL, PL/SQL, PostgreSQL, Kafka, MongoDB, java, C++, C#, VHDL, Verilog, FPGA Cloud Technologies: AWS, Microsoft Azure, Snowflake. Ticketing Applications: JIRA, Service now. Microsoft Office: MS Word, MS Excel, MS ... - 2023 Nov 01
... Programming Languages: T-SQL,Oracle SQL, PL/SQL, PostgreSQL, Kafka, MongoDB, java, C++, C#, VHDL, Verilog, FPGA Cloud Technologies: AWS, Microsoft Azure, Snowflake. Ticketing Applications: JIRA, Service now. Microsoft Office: MS Word, MS Excel, MS ... - 2023 Nov 01
Fpga Design Full Time
Irving, TX
Skills Summary ASIC/FPGA/SoC Design and emulation ●ASIC design using System Verilog, TSMC library modification for FPGA utilization (primitives), test-benching, following established guidelines, process feedback, design for testability and re ... - 2023 Aug 06
Skills Summary ASIC/FPGA/SoC Design and emulation ●ASIC design using System Verilog, TSMC library modification for FPGA utilization (primitives), test-benching, following established guidelines, process feedback, design for testability and re ... - 2023 Aug 06
Electrical Engineer Design
Frisco, TX
FOUAD ELAYYACH ***** ******* ***** Frisco, TX **035 Home: 972-***-**** Cell: 469-***-**** Email: adx7qd@r.postjobfree.com Experienced ELECTRICAL/FPGA DESIGN ENGINEER with successful record in executing all phases of product development for at least ... - 2023 Jul 10
FOUAD ELAYYACH ***** ******* ***** Frisco, TX **035 Home: 972-***-**** Cell: 469-***-**** Email: adx7qd@r.postjobfree.com Experienced ELECTRICAL/FPGA DESIGN ENGINEER with successful record in executing all phases of product development for at least ... - 2023 Jul 10
Team Member Intern
Carrollton, TX
... Verilog, Arduino, Java, Assembly, Python, MySQL, Altera, PHP, HTML, UVM Projects: Reaction Timer Self-Created October 2020- November 2020 • The Reaction Timer was achieved with a DE-10 FPGA Board coded in Verilog using Quartus Prime Lite. ... - 2023 Mar 31
... Verilog, Arduino, Java, Assembly, Python, MySQL, Altera, PHP, HTML, UVM Projects: Reaction Timer Self-Created October 2020- November 2020 • The Reaction Timer was achieved with a DE-10 FPGA Board coded in Verilog using Quartus Prime Lite. ... - 2023 Mar 31
Processor Development Engineer
Irving, TX
... FPGA bring up. Others LD script, Makefile. PROFESSIONAL EXPERIENCE Development engineer with 4.8 years of experience in embedded development & in physical layer LTE, 5G. Qualcomm India Pvt Ltd., Hyderabad, India Senior Engineer, June 2021 – June ... - 2022 Oct 17
... FPGA bring up. Others LD script, Makefile. PROFESSIONAL EXPERIENCE Development engineer with 4.8 years of experience in embedded development & in physical layer LTE, 5G. Qualcomm India Pvt Ltd., Hyderabad, India Senior Engineer, June 2021 – June ... - 2022 Oct 17
Assistant Manager Quality Engineer
Plano, TX
... FPGA Implementation Architecture document ●PON VLAN document CAM ●Table document IGMP ●Snooping document ●Understanding the Concept of System Modeling and how to develop packet accurate model in C which was to be used as a Predictor for the RTL. ... - 2022 Sep 28
... FPGA Implementation Architecture document ●PON VLAN document CAM ●Table document IGMP ●Snooping document ●Understanding the Concept of System Modeling and how to develop packet accurate model in C which was to be used as a Predictor for the RTL. ... - 2022 Sep 28
RF Engineering, Data Analysis, CDMA, LTE, 5G, Field Testing
Dallas, TX, 75252
... Chicago, IL 04/2019 – 06/2019 Promoted to RF Engineer II after one year and contracted with Samsung: Sprint FPGA Project. Contributed to the initial deployment of the Sprint 5G network by processing, analyzing and creating ATP reports which ... - 2020 Oct 26
... Chicago, IL 04/2019 – 06/2019 Promoted to RF Engineer II after one year and contracted with Samsung: Sprint FPGA Project. Contributed to the initial deployment of the Sprint 5G network by processing, analyzing and creating ATP reports which ... - 2020 Oct 26
Engineer Network
Dallas, TX
... Vending Machine Using FSM Designed a Finite State Machine for Vending Machine functionality, implemented the state machine using a VHDL program and tested the design in Intel® Cyclone® 10 GX FPGA Device. Design of Multiplexer Designed a multiplexer ... - 2020 Sep 07
... Vending Machine Using FSM Designed a Finite State Machine for Vending Machine functionality, implemented the state machine using a VHDL program and tested the design in Intel® Cyclone® 10 GX FPGA Device. Design of Multiplexer Designed a multiplexer ... - 2020 Sep 07
Junior Standing in Electrical Engineering
Dallas, TX
... Methodist University, Dallas, TX Fall 2019 Programmed logic circuits in Verilog, using Vivado, then implemented them onto FPGA board: - Built a MUX from a full adder combined of two half adders - Demonstrated Hamming Codes for single bit error ... - 2020 Aug 18
... Methodist University, Dallas, TX Fall 2019 Programmed logic circuits in Verilog, using Vivado, then implemented them onto FPGA board: - Built a MUX from a full adder combined of two half adders - Demonstrated Hamming Codes for single bit error ... - 2020 Aug 18
Engineer Python
Richardson, TX
... Understood the flow of synthesis for using FPGAs to design systems along with programming of an FPGA microcontroller. Seeking Tutor Problem using Concurrent Thread Oct 2019 - Nov 2019 Implemented a solution using POSIX threads, mutex locks, and ... - 2020 Jul 29
... Understood the flow of synthesis for using FPGAs to design systems along with programming of an FPGA microcontroller. Seeking Tutor Problem using Concurrent Thread Oct 2019 - Nov 2019 Implemented a solution using POSIX threads, mutex locks, and ... - 2020 Jul 29