FOUAD ELAYYACH

***** ******* *****

Frisco, TX **035

Home: 972-***-****

Cell: 469-***-****

Email: adx7qd@r.postjobfree.com

Experienced ELECTRICAL/FPGA DESIGN ENGINEER with successful record in executing all phases of product development for at least 15 years of experience. Strong background in cutting-edge complex designs (system board, and ASIC/FPGAs in VHDL & Verilog). Expertise in Digital Design, Datacom/telecomm, CPLDs/FPGAs), simulation (System level), State Machines, DSPs, PLLs/DLLs (300MHz), and embedded firmware in C & Assembly. Leadership. Good writing & communication skills. Also I am a US citizen and have held Security Clearances dating to February 28, 2009 but that it needs re-activation.

QUALIFICATIONS HIGHLIGHTS

CPLD/FPGA _ VHDL/VERILOG HDL (RTL)

High Speed Digital Design _ 10G Ethernet/Fibre Channel/Infini-band

Telecommunications _ Optics, SONET/SDH/POS, ATM, TDM, IP

Microprocessors/microcontrollers _ Motorola, Intel, embedded firmware (Unix, Win)

DSP _ Design and Algorithm development

Good Communication Skills _ MS Visio, MS Project, Excel, SVN, ClearCase.

SUMMARY

Over 10 years of experience as Electrical Engineer and worked as FPGA/ASIC Design Engineer/Circuit Design Engineer.

Experienced Electrical Systems Engineer with diversified experience in hardware and software design, product development, manufacturing test.

Extensive background in board-level design using embedded processors, CPLD with VHDL and Verilog, optical components, analog and high speed digital signals.

Hardware Design using DSPs TMS320C50/C30 _ No coding.

Diagnostics programming and embedded firmware in C & Assembly for microcontrollers.

Embedded 8051 microcontroller design, power design and verification in the lab.

Designed, developed and Schematic capture and PCB Layout (Cadence CIS16.6 & Altium v2015) for night vision systems & industrial controllers

Designed FPGA (Xilinx, Altera, and Igloo & Libero) and verification with VHDL & Modelsim.

Familiar with DO-254 design assurance concepts.

Engaged in ESD, EMI design according to commercial/military standards and compliance testing.

Hands on experience in PLCs, ladder logic sketch, and control panel interface, system alarm electronics using Intel 8051, Moto micro 68HC11, OrCAD for schematic & PCB layout.

Technical Skills:

OS Platforms HP-UX, Linux, DOS, MS Windows, Solaris (UNIX)

CAD Tools Cadence CIS 16.6/Allegro (PCB Layout Directives), Mentor Graphics

XDesigner2015/BoardStation/Pads 9.5, Signoise, PSPICE, Matlab,

SpectraQuest, Orcad/Allegro (Schematics/PCB), Altium (Schematics/Layout),

Microsoft Office (Word, Excel, Power Point, Visio, Project Management),

Xilinx ISE/Vivado, Xilinx Chipscope as built-in ILA, Altera Quartus II, Altera/Intel Signal Tap as ILA in Aria10 FPGA, Actel Libero, Synopsis Synplicity Pro, Mentor Graphics ModelSim and QuestaSim for CPLD/FPGA design

Test Lab Equipment Oscilloscopes, DMM, Counters, Network Analyzers, Signal Generators, Logic

Analyzers, Spectrum Analyzers and Power Meters

Languages RTL (VHDL, Verilog), Test Bench (direct and UVM at FreeFlifght Systems),

C/C++, Assembler, Bourne & C, Shells, Perl, Tcl, Makefile

Specialties_Hardware FPGA/CPLD, Motorola high-performance 32-bit microprocessor 68040, 68HC11 (8-bit micro), Intel 8051 (8-bit micro), optical encoders, avionics, FLIR Night vision sensors, and LCD with bus protocols USB, I2C, SPI, RS-232, RS-485, UART, HDLC & SDLC and Ethernet. Also designed with linear & switching power regulators

Specialties_ Software Embedded firmware in C++ and assembly (UNIX, Linux, Windows)

Technologies T1, E1, SONET Mappers (OC-3/-48/-192), OTN, Network Processors,

Optical Transponders, DWDM, TDM switches, ATM, A/D & D/A

Conversion

Project Configuration Subversion (SVN), Clear-Case, Git, SQL for project archiving, MS Project, MS

Visio, Excel and Power Point

Education: Bachelor in Electrical Engineering from University of Oklahoma, Norman, OK.

Masters in Electrical Engineering from University of Arkansas, Fayetteville, AR

Assumed Team Leadership positions at Nortel, DRS Infrared as well as BEI

Technologies.

PROFESSIONAL EXPERIENCE

North Star Scientific Corp., Oklahoma City, OK 73118 May 2022- Present

Sr. FPGA Electrical Engineer

Design and development of RF Phase Array Antenna network using Xilinx RFSOC Spartan 7 FPGA for the AWACs Radar System. Used DDR4 and DSP IP for high speed communication as a Linux embedded system based on the Xilinx PetaLinux.

Coded RTL in VHDL

Used Vivado IDE and developed test benches for VHDL verification and used Modelsim for simulation.

Mavenir, Inc. Richardson, TX Dec. 2021 – Feb. 2022

Sr. FPGA Electrical Engineer

Design and development of 5G MIMO radio network using Xilinx MPSOC/RFSOC 6048 FPGA. Used DDR4 and DSP IP for high speed communication.

Coded RTL in VHDL

Used Vivado IDE and developed test benches for VHDL verification and used Modelsim for simulation.

Used Git BitBucket for project version management.

Viavi Solutions, Inc. Wichita, KS July 2020 – September 2020

Sr. Principle FPGA Electrical Engineer (Remote Contract- DB)

Design and develop avionics VME based test instruments using high speed PCIe bus, DDR IP, embedded ARM core (HPS) in Intel/Altera Aria 10 SOC FPGA in a system developed in Qsys/System Platform for partial reconfiguration design (PR) and coded in VHDL RTL.

Used Quartus II 64-Bit version 15.0.2 2015 and developed test benches for VHDL verification and used Modelsim 10.4 for simulation.

Diagnosed system using Signal Tap logic analyzer for verification

Used GitLab for project version management.

Between Jobs, TX January 2020 – June 2020

Due to COVID-19.

FreeFlight Systems, Irving, TX June 2019 – January 2020

FPGA Electrical Engineer (Contract)

Design and develop avionics communication digital data links, transponders/universal access transceivers (UAT) in civil aircraft radios, radar altimeters, and GPS for both ES 1090 and ES 5780 communications Automatic Dependent Surveillance – Broadcast (ADS-B) for airplane tracking using

Altera Cyclone V in VHDL and Verilog RTL, DSP algorithms for navigation such as CORDIC, and Digital filters (FIR/IIR), and DO-260A/-250 standards.

Used UVM in a limited role to verify functional behavior in a small test environment for a RX_1090_SNIFFER module that would detect the Preamble of a squitter message transmitted from an airplane to ground station as it approached the airport. The message included airplane altitude, speed, velocity, and GPS location.

Used Quartus II 64-Bit version 15.0.2 2015 and developed test benches for VHDL verification and used Modelsim 10.4 for simulation.

Used TCL, C++ and some python scripts for modeling of External Squitter data links.

Used specs based on the ‘Minimum Operational Performance Standards (MOPS) for airborne equipment for Automatic Dependent Surveillance-Broadcast (ADS-B) AND Traffic Information Service-Broadcast (TIS-B) utilizing 1090 MHz Mode-S Extended Squitter (1090ES)’.

Familiar with RTCA DO-254 process and FAA compliance process.

Raytheon, Marlboro, MA April 2019 – June 2019

FPGA Electrical Engineer (Contract_TP)

Design and develop advanced extreme frequency modem for aerospace applications using Xilinx Ultrascale FPGAs and Intel FPGA.

Also developing high speed Ethernet interfaces with convolution encoder/decoder with interleaving and de-interleaving modulation/demodulation.

Fujitsu Corp., Richardson, TX Aug. 2017- March 2019

FPGA Electrical Engineer (Contract)

Design and develop high speed Ethernet OTN communications in the 1 Gbps-10 Gbps using Xilinx Ultrascale FPGAs such the Kintex and Virtex 7.

Also developed DDR3 phy interface (M256K1769E) using MIG as well as Ibert transceivers for testing fiber optics communication channels with Chipscope ILA in the lab.

Used Xilinx Vivado 2016.3 and developed test benches in Verilog verification and used Cadence SimVision IES for simulation.

Advanced the design process through use of scripts and innovative design methodology that reflected on time savings for the company.

Orbital ATK Corp., Dulles VA Sept.2016 – June 2017

FPGA Electrical Engineer (Contract)

Design & develop rad hardened FPGA for payload satellite application platforms. Designing, implementing, and simulating satellites such as the STP Sat-6 and Cygnus for NASA. Using Virtex5 and Microsemi/Actel RTAX Accelerator FPGAs to implement communications for the flight spacecraft and used such tools as QuestaSim, Aldec Riviera Pro simulator for verification, Synopsys Synplify Pro for synthesis, and developed the RTL (VHDL) in the Vivado2015/ISE 14.7 and Actel Libero IDE.

Used tools such as QuestaSim 10.4, Synplify Pro v10.0, and Libero IDE 9.2.

Implemented innovative design processes through use of scripts and good engineering practices for time savings.

Harris Inc., Ft. Wayne IN Oct. 2015– July 2016

ASIC/FPGA Engineer (Contract)

Design, development of rad hardened FPGA for geospatial applications. Designed, simulated and

Implemented a Green gas observation satellite (GOSAT) for NASA. Used RTAX2000 FPGA to implement the flight spacecraft with implementation of Microsemi CorePCIF version 3.6 for the PCI Data Bus Interface to instrument Panel. The PCI interface was a 32-bit implementation. Also used a variety of tools such as Modelsim & Questasim for verification, Synopsys Synplify Pro for synthesis, and developed the design in VHDL in the Actel Libero IDE.

Used tools such as QuestaSim 10.2b, Synplify Pro v10.0, and Libero IDE 9.2.

Implemented good engineering practices in the design process through use of scripts that saved time & cost in engineering development phase.

Siemens, Irving TX April 2015 – Sept. 2015

Systems Engineer (Contract)

Design, development and schematic capture (Mentor Graphics DxDesigner 2015) for logistical postal mail and baggage sorting control automation. Designed and tested embedded PC computer boards using embedded processors and Cyclone IV FPGAs.

Used Altera Quartus II and VHDL for control FPGA.

Dril-Quip Inc., Houston, TX Sep 2014 – March 2015

Sr. Electrical Engineer

Design, development and schematic capture and PCB Layout (Altium2015) for subsea control automation for oil drilling and process monitoring and hydraulic valve control using sensors.

Used protocols such as RS-485, USB, I2C, RS-232, and UART.

Embedded 8051 microcontroller design, power design and verification in the lab.

Coded communication algorithms in C++.

Debugging and testing of circuit card assemblies and write Technical documentation.

Saved the company on the project development.

Cabello Enterprises, Dallas, TX Jun 2011 – Aug 2014

Sr. Electrical Engineer

Automation _ System design, development and Schematic capture and PCB Layout (Eagle) for home automation in process monitoring and control (relays) using wireless networked sensors.

Used protocols such as ZigBee, USB, I2C, RS-232, RS-485, and UART.

FPGA design (Igloo) and verification with VHDL & Modelsim.

Debugging and testing using scripts.

Wrote Systems requirements & Technical documentation.

DRS Infra-red Technologies, Inc., Dallas, TX Jun 2009 – May 2011

Sr. Electrical Design Engineer

Worked on Hardware design and development of printed circuit board (PCB) assemblies (CCA) using CIS 16.6 Cadence/Allegro and PADS for schematic capture and PCB layout, testing, troubleshooting, system integration (Hardware/firmware) and manufacturing support for imaging technology for both military and civilian aircraft. Also used PSPICE for circuit and noise simulations.

Designed and implemented multiple PCB and flexible circuit card assemblies for various infrared camera (FLIR) and thermal imaging products including night vision goggles and a stand-alone night vision targeting location and designation system for the military.

Major components included in the design _ Cooled and Uncooled IR CMOS sensors, TI DSP Processor (TMS320C6748), Intel 8051 microcontroller, Flash & Mobile DDR (LPDDR) SDRAM (Micron) as well as mixed logic design with A/D and D/A conversion.

Worked with Flash & DDR memory (Micron) as well as mixed signal logic design. Applications include Night Vision, analog signal conditioning using opamp, DC-DC power supply design modification, linear & switching power regulators, A/D & D/A conversion, FPGA (VHDL) video processing for air and land vehicles & other military targeting platforms_ Infrared video capture and processing (NUC Algorithm) using Mid-wave (MW, 3-5 um) and Long-wave (LW 8-12 um) Avalanche photo detectors such as CMOS sensors.

Rockwell Collins, Richardson, TX Feb 2006 – Feb 2009

FPGA/ASIC Design Engineer (Security Clearance) –c2i=CMD, CNTRL, INTEL

Participated in the design and development of tactical TDRS software based radios for various military platforms.

Designed and simulated FPGAs for cryptographic and Information Assurance subsystems.

Performed FPGA design and verification for Altera Stratix II and Cyclone III FPGAs as well as Xilinx Virtex Pro FPGA

Developed RTL coding in VHDL, conducted verification with Modelsim, coded test benches and procedure packages, synthesis with Synplify Pro and place & route with Quartus II (Stratix II, Cyclone III) and Xilinx ISE (Virtex) including static timing analysis and timing closure.

Implemented DSP communication algorithms (CPM Modulation, FEC, interleaving, Correlation) in FPGAs developed with Catapult C and Matlab and familiar with System Verilog.

Wrote VHDL RTL code, test benches, Modelsim simulation, Synplify Pro for synthesis and verification. Also used Xilinx Chipscope as built-in ILA.

Developed test plans, test cases in the verification of top as well as lower level sub-blocks that cross referenced requirements in a traceability matrix.

Verified Ethernet packets and other communication protocols as well as security Algorithms using modeling and BFM (Bus Functional Models).

Conducted Requirements capture and peer review, and developed technical documentation, design verification, and test specification.

Used ClearCase and Subversion for project version tracking and archiving.

BAE Systems (Formerly Boeing), Irving, TX Sep 2004 – Feb 2006

Circuit Design Engineer

Designed and sustained avionics electronics for Boeing airplane fleets (767 etc.) in a manufacturing environment.

Modified and tested FPGAs (VHDL) using Quartus II to upgrade obsolescent logic.

Carried out system diagnostics for obsolescence on existing PCB boards using test temperature chambers, vibration and board scanning to correct any cracked traces with high powered microscope.

Conducted testing, system integration, root cause analysis and corrective action

Used black belt Six Sigma methodologies.

BEI Technologies, Little Rock, AR Apr 2003 – Sep 2004

Sr. Electrical Engineer

Designed, implemented and tested high precision optical encoders and sensors for Aerospace (Satellite, airplanes), and military targeting application for tanks and ships.

Developed FPGA design in VHDL using rad hardened Actel ProASIC and testing of Optical encoders and verification.

Performed Schematic capture (Altium Protel 99) and PCB layout as well as prototyping in the lab.

Wrote technical documentation for various optical encoders, acted as a team leader and interfaced with the customers and increased sales.

Yotta Networks, Plano, TX Aug 2001 – Aug 2002

Electrical Design Engineer

Participated in the design and development of optical routers.

Developed FPGAs (VHDL) that processed SONET transport/path headers for SONET payloads and SONET/SDH Mappers (OC-48 and OC-192), optical transponders, TDM, DWDM PCB testing, and integration.

Debugged designs and tested optical transponders and saved the company by debugging the units and improving the designs.

Nortel Networks, Richardson, TX Jan 2000 – Aug 2001

Sr. Electrical Engineer

Developed the UTOPIA Bridge FPGA saving $20K per Xilinx XC3000 IP core (Two cores required) with big cost savings. The UTOPIA Bridge FPGA Converted Falcon packets generated from a legacy ASIC to ATM packets.

Participated in the design and development of a wireless CDMA platform (Passport) that generated SONET based communications to/from Base Station tower Controllers.

Designed and developed the TDM/ATM/SONET mapper interfaces for the wireless CDMA Passport platform using Network Stream Processors from PMC-Sierra (ATM/IP/TDM), T1/E1/DS1/DS3. SONET/SDH Mappers (TDM/ATM to OC-3), TDM Bandwidth allocators, optical transceivers, power supervisory manager, and PLLs.

Designed and developed FPGAs (UTOPIA master/slave), Verilog, and Synplify for synthesis, Xilinx, and Modelsim simulation & verification.

Coordinated design & tests, and was leading subject-matter expert and team leader in the optical communications side of the design.

Performed system integration, wrote Test Procedures, and System Design Spec in Frame Maker.

Alcatel USA, Plano, TX Jun 1995 – Jan 2000

Sr. Electronic Design Engineer

Designed and developed optical broadband telecommunication systems and digital narrow band cross-connects.

Created innovative designs using such technologies as Mentor Graphics & Cadence (Schematics & PCB Layout), T1/E1, SONET/SDH (OC-12, OC-48), FPGAs (Altera, Xilinx, Actel), VHDL, Synopsys synthesizer, 32-bit microprocessors (Motorola MC68040/MC68360 QUICC), Optics communication transceivers, PLLs, high speed logic (PECL & LVDS).

Participated in the testing & System Integration using high speed Digital Storage Oscilloscopes, digital Logic Analyzers, PCs as host for downloading tests via an Ethernet prototyping board and in-circuit debug emulator (BDM).

Wrote systems specs and test procedures (Interleaf 5).

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