Processor Development Engineer

Udhayabanu Dhanasekaran

Contact number: +1-469-***-**** / +1-682-***-****

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linkedin.com/in/udhayabanu-dhanasekaran-2bb95411b/ CAREER OBJECTIVE

To secure a challenging position in a reputable organization to expand my learnings, knowledge, and skills. TECHNICAL SKILLS

Programming

Language

C Programming

Tool and Debugger Trace32 Lauterbatch for ARM processor, ZView debugger, DVE waveform analyzer, Logical analyzer, Andesigth IDE, Virtual Platform, Spike simulator, ZSP simulator, RUMI

Domain of interest Physical layer, System (soc) architecture, processor. Study and practical

experience

Processor architecture: (Zsp900m, Arm CortexR4, Andes RISCV), hexagon, vector mapping, cache property, cache miss, cache hit, system timer, interrupt controller, RICSV ISA, Dis-assembly, watch dog timer, real time clock, local memory, stack memory, exception.

OS concept: semaphore, mutex, context switch, IPC, RTOS 3GPP specification and IEEE 802: FAPI P5, CAT-M (UE), LTE (eNb), NR physical layer (gNb and ORAN split), WLAN OFDM, HT, VHT, HE (AP) physical layer, NCS, fading ISI, delay spread, reference signal, channel estimation, RFIC, FCC Module worked FAPI P5 module 5G gNb, CAT-M PSS cell search, LTE PUCCH, NR (SSB, PUCCH, PDCCH); SoC chip bring up, cycle and memory level optimization. 802.11n, 11ac, 11ax Rx and Tx SIG field Physical channel processing; FPGA bring up. Others LD script, Makefile.

PROFESSIONAL EXPERIENCE

Development engineer with 4.8 years of experience in embedded development & in physical layer LTE, 5G. Qualcomm India Pvt Ltd., Hyderabad, India

Senior Engineer, June 2021 – June 2022

Project: NR chipset product development ORAN

Contribution: FSM for FAPI p5 module, verification in VP and RUMI. Integration with Fapi P7 module and Tenx (DSP) module

- FAPI p5 non-supervisory PHY FSM implementation for config procedure, verified in VP and in RUMI

- off-target the post processing validation of TC execution

- worked on a new setup CAPLR for 3way integration in RUMI EdgeQ Wireless Pvt Ltd., Bangalore, India

Member of Technical Staff, Feb 2020 – May 2021

Project: NR chipset product development ORAN

Contribution:Verified polar coding & small block coding HW block for control channel SSB, PDCCH, PUCCH with implemented FW in CoSIM

- SSB, PDCCH and PUCCH: Compute the spec defined params like encode/decode bit, rate match, scramble, modulation used for the channel from higher layer interface.

- PUCCH: Captured low level design for processing code, command queue handling and response to L1, program, hardware handle ISR;

Implemented design with CSI demultiplexing as per 3GPP, verified the vector matching in VP

&CoSIM.

- Profiled the FW load and proposed new proposal in system architecture to meet the system requirement. Project: WLAN chipset product development AP

Contribution: LDPC and BCC coding HW block vector matching; FW implementation for SIG field decoding for 11n, 11ac, 11ax; FPGA bring-up support

- Control BCC (SIG decoding): Documented low level design for SIG field decoding; Implemented the SIG field processing and verified in CoSIM.

- Performance analysis: Understood the equivalent dis-assembly ISA for the FW code; Did cycle level optimization; Request new hardware proposal in system

- FPGA bring up: Supported on debugging issue in FPGA bring-up for Tx and Rx data processing (LDPC and BCC);

MBIT Wireless Pvt Ltd, Chennai, India

Development Engineer, July 2017 – Jan 2020

Project: CAT-M product UE

Contribution: PSS cell search module firmware design, implemented FSM to program hardware, handle ISR; Supported SoC bring-up (IFFT/FFT, golden scrambler sequence generation)

- Documented the FSM design for PSS, reviewed and implemented PSS algorithm; Verified the flow in ZSP simulator; Vector matched for tape-out test case; supported debugging issue in FPGA bring-up

- Verified the SoC block FFT/IFFT, scramble sequence generation and supported on debugging using Logical analyzer.

Project: CAT-4 Framework development UE

Contribution: Designed the system recovery framework -recover system from unknow state; Interfaced with Watch dog timer; Logging required debug variables

- Established recovery handling in user and interrupt mode. Established thread switch flow for dumping error information for future analyze, by requesting new proposal to dependent modules.

- Integration of application with framework and provided debugging support to InterTeam EDUCATION

Pursued ECE at MIT, Anna University with a CGPA of 9.0 in May, 2017. Completed Higher Secondary education in St. Joseph HSS in May, 2013 with 96%. Completed High school in St. Joseph HSS in May, 2011 with 97%.

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