Assistant Manager Quality Engineer

Mitali Mitra Mozumdar

*** ******** ***, ***** *****

Email : **************@*****.***

Mobile: +1-214-***-****

WORK EXPERIENCE:

OSP QUALITY ENGINEER at CYIENT

My contribution:

●Responsible for quality assurance, corrections and design delivery to the customer.

●Involved in the quality check of Joint pole jobs.

●Routing of California JPA jobs using MIC

OSP ENGINEER at STARTECH NETWORKS (Contract for AMDOCS)

ARAMIS DESIGN FOR AT&T

My contribution:

●Aramis design, document, Outside Plant Fiber Optic Cable (Underground, Aerial and Buried) and Manhole and Conduit design for ASE jobs.

OSP Engineer at FlexSolv Networks

Aramis design for AT&T

My contribution:

●To do ASE site visits and update ASE Database

●Aramis design, document, Outside Plant Fiber Optic Cable (Underground, Aerial and Buried) and Manhole and Conduit design for ASE and civic jobs.

●Supports the design and planning of new construction as well as the removal/rearrangement of existing fiber optic cables, manholes and conduits

●Contribute to the AutoCAD design for the ASE jobs.

●Coordinate with various cities time to time for acquiring ROW permits.

●Also involved in various project management.

●Look for different bids

●Familiar with ORCA, MIC, JAM, OPTI-NT

●Done design for CRAN jobs to support 5G network

Assistant Manager at Wipro March-2011 to March-2014

●Responsible for delivering VLSI trainings to Rookies and Junior Engineers.

●Preparing training materials and conducting assessments.

April 2021 – TILL DATE

Dec 2020 – April 2021

April 2018 – Nov 2020

April 2010 - Feburary-2011

Verification Engineer at Wipro

Chip level verification of Multimedia Application processor (Client – Texas Instrument)

My contribution:

●C-based verification for the SOC built on ARM and DSP processors.

●Involved in the verification of Subsystem - MMCHS, Efuse and so on. Preparation of Test plan and verification plan document.

●RTL simulation and Debug. GLS Debug

●Scripting for Efuse verification.

●Toggle coverage Analysis.

Design Engineer at Wipro

May 2009 - April 2010

Design, Implementation and Verification of SONET LINE (Client – PMC Sierra)

My contribution:

●Understanding the RS of the Telecom chip and how SONET LINE will be functioning and placed in the whole chip.

●Prepared the Engineering document and the spreadsheet specifying different clock muxing.

●Implemented the Design as per the Engineering document. Ran HAL for Lint checking

●Updated the design with the review comments. Generated DFT Wrapper for the SONET LINE

●Supported SONET verification

●Developed test cases and debugged for Interrupt checking of all the TSBs in DMI, ESSI, SONET_HOPP, SONET and SONET LINE subsystems. Developed test cases and debugged for LCLK/TIP checking of all the TSBs in DMI, ESSI, SONET_HOPP, SONET and SONET LINE subsystems.

Verification Engineer at Wipro

July 2006 – March 2008

Validation of 16/32 BIT RISC MICROCONTROLLER (LEO) (Client – Texas Instrument)

My contribution:

●Understanding the LEO Specification as well as the platform architecture.

●Understanding the following modules : HET

●ADM SMC A7ESRAMW SPLITPWR

●Writing testcases for validating the hookup of these modules. Running the RTL as well as Netlist Simulations

●Preparing the Validation document of the device.

Design Engineer at Wipro

Design and Enhancement of ARM 7 RAM Wrapper Controller (Client – Texas Instrument)

My contribution:

●Understanding the A7ESRAM Wrapper specifications and modifying the same for the enhancements.

●Understanding the existing design of ARM7 RAM Wrapper controller.

●Implementation of the enhancements.

●Debugging the module for the bugs reported by the customer for the existing code.

●Formal verification using formality/ Verplex

●Synthesis done at 100 MHz

●Prepared Design Documentation for ARM7 RAM Wrapper Controller

C modeling Engineer at Wipro

Delivering first-time-right integrated EPON system solution in 19 weeks (Client – Centillium)

My contribution:

●Understanding of the following Specifications / Standards : IEEE 802 LAN/MAN Specifications

●EPON Specifications

●COLT functional specifications

●COLT FPGA Implementation Architecture document

●PON VLAN document CAM

●Table document IGMP

●Snooping document

●Understanding the Concept of System Modeling and how to develop packet accurate model in C which was to be used as a Predictor for the RTL.

●Analysis of various design alternatives in C and splitting up into small functions the various bridge modules for the ease of implementation and debugging.

●Developed the pseudo code before starting the actual C coding.

●Coding was done in a modular way so that the same functions can be reused for both the MUSTANG and COLT bridge

●Testing the RTL as well as the predictor for its functionality

●Written about 40 test-cases in Vera for the LPU block.

Verification Engineer at Wipro

Validation of Multi-port Memory Controller PL175 (Client – ARM)

My contribution:

●Understanding of the Specifications of PrimeCell MPMC provided in the Technical Reference Manual provided by ARM and memory datasheets for the supported memory devices from different vendors.

●Defining of Validation strategy and development & documentation of the validation plan.

●Testing the RTL for its functionality.

●Netlist simulations for the static timing analysis.

●Documenting the validation suites.

Assistant Manager at Wipro March-2011 to March-2014

Responsible for delivering VLSI trainings to Rookies and Junior Engineers.

Preparing training materials and conducting assessments.

Assistant professor at Hitkarini College of Engineering and Technology, Jabalpur August-1997 to August 1999

EDUCATION:

Masters of Science in Microelectronics

GPA : 7.35/10

BITS, Pilani,India

May 2005

Diploma in VLSI

GPA : 7.5/10

CDAC, Nagpur, India

May 2000

Bachelors in Electronics and Tele-communication Engineering

GPA : 77/100

Bhilai Institute of Technology, Bhilai,India

July 1996

Skills:

Hardware

: ARM Processor

Software

: C, Arm Assembly, C Shell, Vi Editor, Perl.

OS

: Unix, Linux

HDL Languages

: Verilog, VHDL

HVL Language

: System Verilog

Simulation Tools

: Model-Sim, gcc compiler, gdb debugger, Verilog XL, NcVHDL, VCS, NcVerilog (Cadence- Affirma).

Synthesis Tools

: DC Shell

Linting Tool

: Leda (Synopsys),Spyglass

Equivalence Checking

: Formality (Synopsys), Verplex

Memory Modeling

: Denali’s Mem-Maker

Waveform Analyzer

: Signal Scan (Cadence-Affirma), UnderTow,Simvision and modelsim

Coverage Tools

: V-Navigator (TransEda), HDL-Score(Innoveda)

Version Control

CVS, Synchronicity, Clearcase Management Tool

Domain Exposure

ARM AHB and AXI architecture

Testing Methodology for ARM Prime-Cell development

Preliminary of IEEE 802.11, EPON system, OMAP2420, ARM1136

ETM (Embedded Trace Macrocell)

ETB (Embedded Trace Buffer)

Emulation and JTAG protocol

TMS470 Platform Architecture

Certification:

●Formality

●FPGA

●Synthesis

●Analog Layout

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