Skills Summary

ASIC/FPGA/SoC Design and emulation

●ASIC design using System Verilog, TSMC library modification for FPGA utilization (primitives), test-benching, following established guidelines, process feedback, design for testability and re-usability, automation scripts, redesign for timing closure.

●FPGA code: design for place and route, timing optimization, standard modules redesign, clock domain reduction, out of data-flow resource utilization, synchronous reset code re-design, micro-sequencers, uniform VHDL-Verilog target code.

●Simulations with Synopsys Verdi(VCS), Mentor Modelsim, Cadence Incisive, Xilinx Vivado, simulations via TCL automations, simulations of multi-FPGA design environment featuring end-to-end software flow.

●Design Synthesis using Xilinx Vivado/ISE, Quartus II, Actel Libero 7, Lattice Diamond/Synplify, Mentor Leonardo Spectrum.

●FPGA Design on technologies: ARM based SoC, AXI, T1/E1, DS3, STS1, STM0, STM1, ATM-TDM, PCI, PCIX, PCI Express, Xilinx (Micro-Blaze, Aurora, Temac, 10G Mac-Xaui, Mig DDR2-DDR3-DDR4, QDRAM, AXI4), 1G/10G Ethernet, serial to parallel IO/memory/upBus, Free Scale Local Bus up-interface, 32 bit Ti DSP Local bus interface, FPGA internal PLL/DLL, timing de-synchronizers, DAC/SH, ADC, I2C, SPI, CAM, RS232, Serial LCD, clock domain crossings.

●SVN version control, GIT version control, Linux Ubuntu/Centos.

●Use of TCL/Python scripting for design automatizations and automatic version control.

●Design/Architecture of FPGA based electronic products including sustaining with time to delivery, development cycle follow-up with engineering changes, modifications and redesign, system requirements specifications and documentation, various groups documentation review, embedded software and board hardware design tasks interfacing, with emphasis on demo product availability.

Electronics Hardware Design

●Digital and Analog Circuits Design: from Marketing Product Requirement to General Availability - Telecom, Computing and Military industries.

●Responsible for all phases of project flow: development of detailed hw/fpga engineering specs, test plans, verification/testing and debugging report documentation, hw/fpga development, layout recommendation and final prefab product review/changes.

●Design maintenance and redesign for: cost reduction, RoHS compliance, obsolescence, alternate supplier. Root cause analysis and customer problem solving. Integration of product features (software, FPGA and hardware) at design level as central figure of project planning (ONTG).

●Accumulated knowledge in: team leading skills, junior stuff supervision and technology resources.

●Schematic Capture design using ORCAD, DxDesigner and Cadence Concept. Multilayer PCB component placement and routing using Cadence Allegro PCB Editor. Layout constraints entry, PCB stack-up recommendation, trace impedance calculation and signal evaluation, layout approvals, PCB bring-up, lab measurements.

●Design with technologies – ROADM(OCM), 800DDR, 15G XAUI, SPI4.2, RGMII, GMII, MII, Infiniband, TDM, ATM, Ethernet/IP, PCIe5G/PCMCIA, FXS, FXO, T1/E1, DS3/STS1/E3, S155/OC3, ADSL/HDSL2, Echo Cancellation DSP Schemes technology, Video conversion and compression, ASIC IP emulation via Xilinx Ultra-scale FPGA.

●Design with various microprocessors – Qualcomm APQ8016-1-760NSP, Ti Sitara AM335x, Ti CC3200, Cypress CYBLE familiy, ATMEGA, PIC, AMCC 405GP-EX, Cavium-Octeon CN3860 8-16 core at 1GHz, PPC8641 dual core at 1.5Ghz, PPC405GPr_EX, Micro-blaze, MPC 860, CF5282, MPC 8260, MPC 750, IXP1200, C8051, HC6805, HC6811 and Z86, Xtensa LX7.

●Use of Technology Silicon – ALTERA STRATIXII 130GX, Aria10 10A115F40, Max10 10M25, MARVELL8896-8846-883015, POWR1220AT8-UCD9080, DDR2 SDRAM, DDR2 RLDRAM, 800 DDR2 DIMs, PEX8114 PCIX-PCIE Bridge, Ample Redhawk, BCM5461, BCM5466, VSC7326, MPC107, PMC PM4354, PMC PM8313, PMC 8315, PMC PM5342, Conexant CN8395, Transwitch TXC03361, Intel IXF6401, Lu APC6401, Altera X Family, Xilinx FPGA V4,V5,V6, Xilinx UltraScale xcvu095, Xilinx UltraScale+ xcvu9p, Actel and Lattice flash based FPGA, AD9887A, Mellanox Infiniscale III Router at 240Gps and 480Gps, Snap 12 Optical 30-60G transducers, SFP, SFP+, VIDEO SFP, XFI, 28nm HPM and HPC TSMC.

●Database software tools – Agile, Clear Case, ERP, and ORCAD CIS.

Employment History

ASIC RTL/FPGA Design – Moneta Technology – April 2022 till January 2023 (Full Time)

●ASIC RTL Design - Simulations using Synopsys Verdi (VCS-FSDB). ASIC System Verilog RTL.

●FPGA RTL Design - ASIC emulation via Nomachine AWS CLI and Xilinx VIVADO 2019. Product FPGA design (Lattice).

SoC/FPGA Design – Flight Data Systems – July 2021 till April 2022 (Full Time)

●SoC and FPGA Design (DO254) - Design and design change on Cyclone III and Cyclone V SE FPGA. Simulation with Modelsim, Synthesis with Intel Quartus 10, 13, 16 and 18. Linux bash script for FPGA synthesis automation.

●Support work - Software Test Procedure and Code coverage using LDRA. Hardware Test Procedures. Source control via SVN, GIT and ERP. Linux back door debugging.

SoC/FPGA Design – Flex Medical Irving DFW – August 2018 - May 2021 (Contract)

SoC and FPGA Design

●Design change on Cyclone IV FPGA. Simulation with Modelsim, Synthesis with Intel Quartus 18. TCL script for results verification

●Xilinx Zync 7000 SoC development using Xilinx VIVADO and SDK. Software development for hardware verification

●Source control, review and tracking via Bitbucket and Jira

Hardware and PCB Design support

●Designed number of interface boards for interfacing with off the shelf demo boards

●Reviewed ongoing schematic designs with corrections proposals, designed Orcad Schematic TCL procedures

Software Design

●Used STM32CUBEIDE for H757, H755, L552 and L556 processors featuring c code design.

Design, process and procedures capture

●Captured FPGA Standard Operating Procedure (Proposal, Concept, Development and Verification Process).

●Captured plans for Design validation within company review process (Design Verification, Process Validation, Quality and Document Control Approvals)

●Established SoC Design and Hardware Design Review checklist documentation. Proposed Risk Management Design Architecture for patient’s safety

FPGA Design – Cheetah Networks – January 2018 till June 2018 (Short Term Contract)

10G/1G Ethernet packet reflector FPGA design

●Designed FPGA Target Verilog code and supporting simulation code with TCL scripting automation support code for Ethernet packet pass-through/reflect feature. Design supported Equipment and System side reflect feature. Reflect conditions considered Mac-IPV4-UDP src-dst addresses.

●Generated Verilog code for UART, Register Block, FPGA PLL-s, FPGA FIFO-s, Physical 1G and 10G MAC to logical Ethernet MAC interface, Ethernet packet processing on Src-Dst MAC ADDR Src-Dst IPV4 ADDR Src-Dst UDP Port Number VLAN reflect support .

●Used TCL script for Wireshark packet selection and Verilog compatible file format conversion. TCL script for automated simulation on Model-sim simulation tool. TCL script for simulation results comparison.

●Used Arrow EVEREST-DEV-BOARD – Microsemi FPGA MPF300TS-1FCG1152EES with 1X1Gbe on SFP+ and 3X1Gbe RJ45.

FPGA Design and Evaluation of Third Party IP (ASIC Architecture) – Istuary Innovation Group – November 2016/October 2017 (Permanent)

Architecture evaluation and redesign proposition of third party IP (CAM and TCAM - vendors Renesas and eSilicon)

●Vendor Interfacing for IP features introduction and Specs gathering. Documentation write-up for architecture review. Provided FPGA emulation plan (proposed FPGA development platform for IP implementation, FPGA design procedures and place and route tools automation plan).

●Performed FPGA target code simulation using Cadence Incisive simulator as well as Xilinx simulator. Performed FPGA place and route using Xilinx Vivado 2017.1 tool. Tested bit file on the Xilinx VCU108 development board using JTAG/AXI4 debugging feature.

●Generated documentation describing interface change of vendor IP – to allow vendor IP to run on the FPGA.

FPGA emulation of ASIC sub-modules (secure Ethernet Traffic featuring Cadence and Arteris vendors).

●Generated simulation environment for third party IPs: Cadence Xtensa LX7 micro-processor, Arteris NOC, Xilinx DDR4 Core.

●Performed simulation by running microprocessor binaries thus exercising all the microprocessor interfaces.

●Performed FPGA place and route for VCU108 development board and tested binary configuration on the FPGA. Run microprocessor elf file on the micro-processors via JTAG interface.

●Collaboration on IPs integration/simulation activities – simulation results feed-back to integration team.

●FPGA interfaces and resources used: AXI4, DDR4, AXI4 Block Ram, Block Ram, MMCM 50-300MHz.

Automatizations via design of TCL Procedures for handling:

●Custom project files: configuration files, source code link files, third Party IP vs FPGA IPs selection files

●Automated compilation, simulation and place/route of the FPGA.

●Automated Subversion or Git source files control .

FPGA/HW Design Services – Design1st – January 2014 till November 2016 (Permanent)

Large FPGA DESIGN – Xilinx V5 FPGA design review and FPGA modules redesign – Quad DSP frequency multiplier (FIR filters, CIC…).

●Reverse engineered customer FPGA VHDL code to block diagram.

●Generated simulation environment to pass DSP samples via FPGA resources. Captured result files and reviewed them in FFT format (Sci-Lab). Performed place and route of the FPGA. Debugged FPGA operation using ILA.

●Generated documentation describing FPGA redesign process and proposed solution to customer.

●Using TCL procedures to automate redesign process.

Small FPGA/CPLD DESIGN – Xilinx, Altera and Lattice

●Designed and field tested small flip flop count CPLD/FPGA for various customers.

Hardware Design

●Hardware design of Giga sample+ ADC interfaced to million LAB FPGA (10A115F40).

●Blue-Tooth and Wi-Fi Controlled electronic and electro-mechanical devices.

●Electro-chemical control device utilizing microcontroller, ADCs, GPRS modem and OPAMPS (water quality instrumentation).

●Hardware controls utilizing PIC, ATMEGA and CC3200 microcontrollers.

●Touch sensor arrays utilizing ADC and analog multiplexers.

●Bar Code scanner utilizing 13 mega-pixel camera and Snap Dragon microprocessor (Qualcomm APQ8016 – Snapdragon 410).

●Small electronics power supplies design using Ti Web-bench Designer.

●Fractal WiFi antenna implementation - PCB layout guidance with lab testing utilizing network analyzer.

●Large LED array driver circuits using shift registers and custom power supplies.

●High energy magnetic pulser for medical use (2000 Volt, 7000 Amp), with pulse control box.

●Verification and Standardization on various product lines in accordance with North American and European market standardization (NEMKO CSA approvals).

FPGA Design – D-TA - Feb. 2012 – September 2013 (Permanent)

FPGA Design, Implementations and Verification on Xilinx V5 and V6 FPGAs:

Input blocks

●9 Input ADC, 16 bit, single data rate at 4Megasamples/s with common data acquisition start.

●Quad ADC, 16 bit, single data rate at 160Mega samples/s with common data acquisition start.

●Dual, ADC 12 bit, double data rate at 1800Mega samples/s via IDDR, MMCM and FIFO/DPRAM.

●Single ADC, 12 bit, double data rate at 3600Mega samples/s via IDDR, MMCM and FIFO/DPRAM.

●Aurora 10Gbit 8b10b (64bit/156.25Mhz) with upstream and downstream data flow interrupt handshaking.

●Aurora 8x6.25Gbit 66/64 (8 x 32bit/189.4Mhz or 8x64bit/94.7Mhz) with packet based data flow handshaking.

●10 Gigabit Ethernet Decoder – XAUI Core, Physical Mac Core, Ethernet, IP, UDP and custom Decoder.

Output blocks

●Output DAC, 16 bit, single data rate at 4Megasamples/s with common data playback start and data sync.

●Quad DAC, 16 bit, single data rate at 160Mega samples/s with common data playback start.

●Single DAC, 12 bit, double data rate at 3600Mega samples/s via ODDR, MMCM and FIFO/DPRAM.

●Aurora 10Gbit 8b10b (64bit/156.25Mhz) with upstream and upstream data flow interrupt handshaking.

●Aurora 8x6.25Gbit 66/64 (8 x 32bit/189.4Mhz or 8x64bit/94.7Mhz) with packet based data flow handshaking.

●10 Gigabit Ethernet Encoder – XAUI Core, Physical Mac Core, Ethernet, IP, UDP and custom Encoder.

Register blocks

●Processor based, 80 x 32 bit register block with clock domain designed for timing closure.SPI based, 111 x 16 bit register block with clock domain designed for timing closure.

Data processing engines

●ADC data mux with bit stripping. Configurable 16 bit quarter sine wave block with waveform rewrite option.

●Dual 16 bit Complex oscillator (NCO) with one memory block at 266+Mhz and option of single oscillator configuration.

●FIR low pass filters (32 DDC): 12 bit 24 tap FIR filter (christmas tree flow) with carry-look ahead and carry chain adders.

●ADC data formatting and re-packetization. Data rounding.

●Configurable 40 Gigabit ADC data rate to 4 x 10 Gigabit Ethernet stream separator.

●Configurable 4 x 10Gigabit Ethernet stream concentrator to one 40 gigabit DAC playback channel.

●Configurable dual 34 gigabit DDR3 memory throughput utilization via native core interface.

●Configurable 7 port, 128 bit, switch matrix with packet based muxing at 45Gigabits/s.

●Inter FPGA custom based, high speed serial messaging interface and FIFO data interface.

●Temux based, 1 Gigabit, Ethernet, IP, UDP and Custom Encoder and Decoder with ARP and ICMP.

●Data processing engines

●Product or module functional description, high level block diagram, sub-blocks implementation diagrams, input-output features description, verification instructions sheet.

●Fully automatized, TCL based, end to end Modelsim functional simulations. Bit file lab testing and verification.

Electronics Hardware/FPGA Design – TCS (Ultra Electronics Ottawa) – Jan. 2011 - Feb. 2012 (Temporary-permanent)

RPP UAV mother-board design – VPX back-plane based board design featuring dual V6 SX315T FPGA, dual 1800megasamples/s ADC, Quad Gen2 5Gigabit/s PCIe, Spartan6, dual 128bit DDR3 memory blocks, TI discrete SMPS (1.2V at 40Amps – 70uV ripple rms).

RPP UAV Digitizer Mezzanine board design - ADC12D1800 daughter board with ultra low jitter clock circuit and high noise rejection ratio power filtering.

RPP UAV Configuration FPGA design – control fpga design.

Electronics Hardware Verification – FLEXTRONICS (Cisco SA) – Nov. 2009 till Oct. 2010 (contract)

Hardware verification on Cisco-Scientific Atlanta video set top box products.

Electronics Hardware Design and Verification – JDSU - Nov. 2008 till Nov. 2009 (contract)

ROADM(OCM) Board Design – WSS Wave Ready Product - Free scale Cold fire based control board for reconfigurable optical add-drop multiplexer channel monitoring - ROADM OCM. Board featured SDRAM, FLASH, CPLD, 100Base Ethernet.

Electro-Magnetic Compatibility testing. Radiated and Conducted Emissions, Electro-Static Discharge and HIPOT verification (EMI, EMC, ESD and HIPOT).

Electronics Hardware Designer – CIENA - June 2007 to Nov 2008 (Permanent)

Multi-protocol network adapter - EM6 Board and Control FPGA-CPLD Design

EM6 Product Features - 100MBps-6.25GBps rate adaptable six port network transport mechanism.

Protocols Supported – 1000BT, GE, FC100, FC200, FC400, SONET OC3, OC12, OC48, Raw Video SDI-HDI-HDI/1.001, Infiniband, DDR Infiniband, OTU1, SFP+ rates and custom rates.

Responsibilities as ONTG(one neck to grab)

●Preliminary Design Requirement Documentation.

●Components Selection and Recommendation, adjusting solutions with corporate buyer.

●Timeline document propositions and time-sheet maintenance (Project hardware development cycle).

●Weekly Meeting for Software-FPGA coordination and information sharing document update, follow up on weekly meeting action items and their bring-up to resolution, weekly meeting with organization VP and report on action items.

●DxDesigner Schematic Symbol Capture and Components Database submission, DxDesigner Board Schematic Capture, two shot Schematic Review.

●Electrical BOM and Mechanicals submission to Agile (database), components availability control process and Agile AVL corrections.

●HDI Layout placement design document, constraints capture, placement approvals coordination, routing guidance and problem solutions recommendations, routing approvals.

●FPGA-CPLD Initial Design Document, design review and preliminary design simulation.

●LAB instrumentation preparation for board debugging.

●Board Debugging, FPGA-CPLD debugging, Board Design Verification Documentation, FPGA-CPLD Design Verification Documentation, Source control File submission, Manufacturing Test specification Document, Test Document coordination with Operations, manufacturing process adjustment for board and components fabrication.

●Re-spin process validation, solutions implementation, documentation correction, schematic changes, layout and fabrication realization, debugging and release to GA.

●Existing Product Maintenance – Problem Solving, Solutions Testing, Documentation Ordering, fixes Database updating.

Electronics Hardware Prime – NORTEL - September 2006 to June 2007 (contract)

Dual Multiprocessor multi-core server farm load balancing product design

Responsibilities as Hardware Designer

●Components Selection and Recommendation, Cadence Schematic Symbol Capture, Schematic Capture, schematic review.

●Electrical BOM database entry.

●Cadence layout process control and corrections guidance, layout constraints entry.

●LAB preparation for board debugging.

●Board debugging, Design Verification Documentation, Test Specification Documentation.

Electronics Hardware and FPGA Prime – LIQUID COMPUTING - October 2005 to September 2006 (Temporary-permanent)

Multi-gigabit (240/480Gbps) hardware design for optical and electrical Infiniband and GEthernet interface.

Responsibilities as Hardware Designer

●Components Selection and Recommendation, Cadence Schematic Symbol Capture, Schematic Capture, schematic review.

●Electrical BOM database entry.

●Cadence layout process control and corrections guidance, layout constraints entry.

●FPGA-CPLD Initial Design Document, design review and preliminary design simulation.

●LAB preparation for board debugging.

●Board debugging, Design Verification Documentation, Test Specification Documentation.

Electronics Hardware and FPGA Design Services – NBT TECHNOLOGY Inc - June 2004 to October 2005 (contract).

Product research, design and implementation for various startup and niche companies (Nortel Networks, Curtis Wright-DY4, NewCon Optik, Metconnex, Algolith, Epiphan, Raytheon).

Microcontrollers, FPGA handling of RTC/EEPROM, Multi-Color LCD, FPGA logic analyzers, 3GHz signal sampler PLL, Video conversions and compression.

Software development on Windows and custom platforms using Visual Studio, JUNGO Driver development Kit, custom FPGA microcontroller and microprocessor compilers and various GUIs.

FPGA design in the field of PCI simulations, DAC/SH drive, WDTimers, Interrupt schemes, UART/I2C/SPI/GPIO custom design, Video signal Generators and FPGA Microprocessors.

Electronics Hardware and FPGA Designer - ZHONE TECHNOLOGIES Inc - December 1999 to June 2004 – (Permanent)

Part of the hardware and FPGA development team from the early startup phase in 1998 to the company going public in December of 2003.

Hardware Design

GR303 / DACS gateway (Sechtor 300)

●Prime board level designer for main system cross-connect, enhanced shelf processor and various line cards: FXS/FXO, T1/E1, DS3, STS1, STMO, STM1, OC3, E3, IO, (OC12-48) and main clock card.

●Responsible for high-density board and FPGA design including end-to-end release process (ECOs).

●Only designer responsible to support all cards in the product including field failure investigation and interface with manufacturing.

●Technical documentation and support of software integration.

Multi-service Gateway (BAN)

●Support of existing DSL and ATM/IP SONET line cards.

●Investigated and resolved hardware and FPGA design-redesigns, manufacturing and field problems.

ATM-service Gateway (S100)

●Investigated and resolved hardware design, manufacturing and field problems.

FPGA Design on Altera MAX II Devices

DUAL DS3 to 2400 DSO Cross-connect

●E3/DS3/STS1 bidirectional mapper interface to T1/E1 lanes.

●T1/E1 lanes to double speed DPRAM mapping.

●DPRAM to 2400 DSO cross-connect with configurable channel select.

●HDLC protocol channel map to T1/E1 stream with concurrent DPRAM stream mux.

●DS3/STS1 channel switch with configurable DSO cross-connect.

●DS3/STM1 traffic overhead extraction for serial control traffic monitoring.

●MPC860 parallel bus register block interface with SPI, RS232 and I2C support.

●Blade hot-swap clock edge detect with redundant card activate.

Single STM1/OC3 to 2400 DSO Cross-connect

●STM1/OC3 bidirectional mapper interface to T1/E1 lanes.

●Configurable T1/E1 mapping into 2 DS3/STM1 rate interfaces.

●Configurable, HDLC synced, 2 out of 3, DS3/STM1 rate, port select.

●DS3/STM1 traffic overhead extraction for serial control traffic monitoring.

Electronic Hardware Design Verification on:

●2400 DSO cross-connect board.

●DS3/STS1 channel mapper board.

●STM1/OC3 channel mapper board.

●28T1/21E1 channel mapper board.

●24 FXS/FXO central office port termination board.

●T1/E1/DS3/STS1/STM1/OC3IO boards.

●Clock synchronization board with redundant pair

Electronics Hardware and FPGA Designer – PREMISYS COMMUNICATIONS - August 1998 to December 1999 - (Permanent)

Member of Voice Gateways team = Same as above at Zhone.

Electronics Hardware Designer – NORTEL NETWORKS - July 1997 to August 1998 – (Full Time)

Member of ATM - ADSL - VOICE over ATM Development Team.

●CPE ATM25, Ethernet/IP, Voice over ATM design.

●CO ATM-ADSL analog line-card design.

●CPE ATM-ADSL analog Network Interface Module design.

Electronics Hardware Design and Verification – GANDALF TECHNOLOGIES Ltd - August 1996 to July 1997 (Permanent).

Member of the Remote Access Development Team.

Firmware and Board Level Hardware Designer – ENERSTAT, Ltd - May 1995 to August 1996 – (Permanent).

Member of Programmable Thermostats Development Team.

Board Level Hardware Designer – KIRILO SAVIC, Ltd - August 1990 to May 1995.- (Full Time)

Member of Applications Electronics Team - Research Institute for Industrial and Military applications.

Education - Bachelor of Science in Electrical Engineering - University of Zagreb, Croatia (1985-1991).

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