| Resume alert | Resumes 61 - 70 of 136 |
High School Higher Secondary
Hyderabad, Telangana, India
... Projects Involved: B.Tech Final project entitled “Fpga based design and implementation of qpsk modulator using XSG” in “Akshaya bharathi institute of technology” from kadapa, Andhrapradesh. Skills: Good Interpersonal skills. Strong programming ... - 2017 Jul 19
... Projects Involved: B.Tech Final project entitled “Fpga based design and implementation of qpsk modulator using XSG” in “Akshaya bharathi institute of technology” from kadapa, Andhrapradesh. Skills: Good Interpersonal skills. Strong programming ... - 2017 Jul 19
Network Engineer Technical Support
Secunderabad, Telangana, India
... RESEARCH ASSISTANT AT UMBC, MARYLAND JAN 2016-DEC 2016 Assisted students to performed labs assignments and debugging hardware support for FPGA, VLSI classes. Study of Internet protocols – OSI model, TCP/IP model, DNS, DHCP, HTTP, HTTPS, SSH, Telnet, ... - 2017 Jun 14
... RESEARCH ASSISTANT AT UMBC, MARYLAND JAN 2016-DEC 2016 Assisted students to performed labs assignments and debugging hardware support for FPGA, VLSI classes. Study of Internet protocols – OSI model, TCP/IP model, DNS, DHCP, HTTP, HTTPS, SSH, Telnet, ... - 2017 Jun 14
Engineer Engineering
Hyderabad, Telangana, India
... A well known technique is Distributed Arithmetic (DA), which is used as a very efficient solution especially suited for LUT based FPGA architectures. B.TECH: An Intelligent Ambulance Car Which Controls Traffic Light. PLATFORM: EMBEDDED SYSTEMS. ... - 2017 Jun 13
... A well known technique is Distributed Arithmetic (DA), which is used as a very efficient solution especially suited for LUT based FPGA architectures. B.TECH: An Intelligent Ambulance Car Which Controls Traffic Light. PLATFORM: EMBEDDED SYSTEMS. ... - 2017 Jun 13
Product Development Design
Hyderabad, Telangana, India
... Familiar with Synthesis techniques and Synthesis of Altera & Xilinx FPGA's. Knowledge in CPLD/FPGA/SOPC/ ASIC Design Methodology & verification on test benches using Verilog HDL. PV System Design and development according to project requirements and ... - 2017 Apr 21
... Familiar with Synthesis techniques and Synthesis of Altera & Xilinx FPGA's. Knowledge in CPLD/FPGA/SOPC/ ASIC Design Methodology & verification on test benches using Verilog HDL. PV System Design and development according to project requirements and ... - 2017 Apr 21
Design High School
Hyderabad, Telangana, India
... Technical Expertise CAD for VLSI Circuits, CMOS Mixed Signal Design, Low Power VLSI Design,CPLD & FPGA, CMOS DICD, System On Chip Architecture, Design For Testability, Digital Signal Processors & Architectures, CMOS Analog Integrated Circuit Design. ... - 2017 Mar 14
... Technical Expertise CAD for VLSI Circuits, CMOS Mixed Signal Design, Low Power VLSI Design,CPLD & FPGA, CMOS DICD, System On Chip Architecture, Design For Testability, Digital Signal Processors & Architectures, CMOS Analog Integrated Circuit Design. ... - 2017 Mar 14
java Developer
Hyderabad, Telangana, India
... PROJECT: Title: FPGA Implementation of Advanced Encryption and Decryption Standard. Role: Team Lead and Developer Description: Providing Security for the data by encoding it at the transmission end and decoding at while reception as an original data ... - 2017 Feb 22
... PROJECT: Title: FPGA Implementation of Advanced Encryption and Decryption Standard. Role: Team Lead and Developer Description: Providing Security for the data by encoding it at the transmission end and decoding at while reception as an original data ... - 2017 Feb 22
Microsoft Office Project
Hyderabad, Telangana, India
... APPLICATION : Home applications based on GSM with mobile MAIN PROJECT SHA-1 ALGORITHM USING FPGA Title : DISRIPTION: These “security seals” are becoming more common on commercial sites, as customers have been found to avoid purchasing from companies ... - 2017 Jan 01
... APPLICATION : Home applications based on GSM with mobile MAIN PROJECT SHA-1 ALGORITHM USING FPGA Title : DISRIPTION: These “security seals” are becoming more common on commercial sites, as customers have been found to avoid purchasing from companies ... - 2017 Jan 01
Engineering Design
Hyderabad, Telangana, India
... Basics of JAVA VLSI Domain Skills HDL : Verilog HVL : SystemVerilog EDA Tool : Modelsim and ISE Verification Methodologies : Coverage Driven Verification TB Methodology : UVM Domain : ASIC/FPGA front-end Design and Verification Knowledge : RTL ... - 2016 Oct 28
... Basics of JAVA VLSI Domain Skills HDL : Verilog HVL : SystemVerilog EDA Tool : Modelsim and ISE Verification Methodologies : Coverage Driven Verification TB Methodology : UVM Domain : ASIC/FPGA front-end Design and Verification Knowledge : RTL ... - 2016 Oct 28
Advance Java, .NET, SQL, Oracle, MS Office.
Hyderabad, Telangana, India
... web essentials, Embedded C Software Tools: : Mat Lab, Keil Micro Vision, Xilinx ISE PROFESSIONAL SKILLS: Zeal To Learn New Things Quick Learner Innovating Thinking Team spirited PROJECTS: Title: A Compact AES Core Encryption by using Xilinx FPGA. ... - 2016 Oct 24
... web essentials, Embedded C Software Tools: : Mat Lab, Keil Micro Vision, Xilinx ISE PROFESSIONAL SKILLS: Zeal To Learn New Things Quick Learner Innovating Thinking Team spirited PROJECTS: Title: A Compact AES Core Encryption by using Xilinx FPGA. ... - 2016 Oct 24
Professional Experience Design Engineer
Hyderabad, Telangana, India
... EDA Tools : Modelsim, Xilinx ISE Design Suite, Questasim, Cadence Domain : ASIC/FPGA Design Flow, Digital Design concepts Knowledge : RTL Coding, FSM based design, Simulation, Code Coverage Verification Methodologies : Coverage Driven Verification. ... - 2016 Mar 25
... EDA Tools : Modelsim, Xilinx ISE Design Suite, Questasim, Cadence Domain : ASIC/FPGA Design Flow, Digital Design concepts Knowledge : RTL Coding, FSM based design, Simulation, Code Coverage Verification Methodologies : Coverage Driven Verification. ... - 2016 Mar 25