A.SWETHA

M.Tech in VLSI System Design, Mobile: +91-944*******

H.No-10-33/1,Vinayaknagar, Balanagar, Email: acy92v@r.postjobfree.com

Hyderabad,Telangana,500042.

Objective

Seeking a position with an organization where I can contribute my skills for organization’s success and synchronize with new technology while being resourceful, innovative and flexible.

Skill Set

EDA Tools :Cadence synthesis tool.

Hardware Description Languages : Verilog.

Software Skills : C, java.

Platforms : Windows.

Assembly Programming : µP 8085.

Mathematical Tools : MATLAB.

Technical Expertise

CAD for VLSI Circuits, CMOS Mixed Signal Design, Low Power VLSI Design,CPLD & FPGA, CMOS DICD, System On Chip Architecture, Design For Testability, Digital Signal Processors & Architectures, CMOS Analog Integrated Circuit Design.

Academic Profile

Degree

Board / University

Year

CGPA / Percentage

M.Tech [VLSI System Design]

Malla reddy Engineering College

2016

82.06%

B.E [ECE]

MRCET

2014

77.60%

Intermediate[MPC]

Narayana Junior College

2010

79

SSC

N.S.K.K High School

2008

79

Achievements

Secured Score of 346 with 18863th rank among 172714aspirants in GATE’ 15.

Presented a Paper on Design of sequential elements for low power clocked systems.

Attended workshop on Mixed Signals &Verification using CADENCE tools.

Secured cent in mathematics in B.Tech.

Project-design & implementation of single & double precision multipliers using kogge stone adder

Floating point multiplication is a crucial operation in high power computing applications such as image processing, signal processing etc. And also multiplication is the most time and power consuming operation. This paper proposes an efficient method for IEEE 754 floating point multiplication which gives a better implementation in terms of delay and power. A combination of Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm (Vedic Mathematics) is used to implement unsigned binary multiplier for mantissa multiplication. The multiplier is implemented using Verilog

HDL, targeted on Spartan-3E and Virtex-4 FPGA.

Personal Strengths

Hard working and good at team work.

Rapid at learning things.

PERSONAL DOSSIER

Name : A.SWETHA

Father Name : A.NAGESHWAR RAO

DOB : 26 March 1993

Gender : Female

Nationality : Indian

Marital Status : Unmarried

Languages : English, Hindi, Telugu.

Hobbies : Playing Chess, Painting.

Place: Hyderabad

Date: A.SWETHA

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