Professional Experience Design Engineer

Gali Venkata Sai Ravi Teja

Mobile No: +91-741******* E-mail: **************@*****.***

Career Objective:

To achieve professional excellence and enhance my knowledge in the field of VLSI by joining with dynamic motivated team that works towards the growth of the organization, and can utilize my skills and knowledge in any organization.

Professional Experience:

Working as a RTL Design Engineer at Cognos IT Solutions Pvt Ltd- Hyderabad from 1 year to till date.

Technical Skills:

HDL’s : Verilog and VHDL.

HVL : System Verilog.

EDA Tools : Modelsim, Xilinx ISE Design Suite, Questasim, Cadence

Domain : ASIC/FPGA Design Flow, Digital Design concepts

Knowledge : RTL Coding, FSM based design, Simulation, Code Coverage

Verification Methodologies : Coverage Driven Verification.

Training Qualification:

Diploma in Advance VLSI Design in Wingsvision Techno for 3 Months.

Educational Qualifications:

B.Tech-2014 in Electronics & communication from JNTU Hyderabad Passed with 68%.

Intermediate-2010 in MPC from State Board of Intermediate with 83%.

Matriculation-2008 from secondary state board passed with 79%.

Major Strengths:

Effective communicator - Can communicate ideas with a wide range of people

Quick learner and hardworking

Flexible and adapt quickly to new working environments

Work independently and as part of a team & Strong determination to succeed.

Project Details:

1. Title: Designed a Test pattern generator by using LP-LFSR.

Description:

In this project I had designed a LP-LFSR (Low Power Linear Feedback Shift Register) which is used as a test pattern generator to generate the test patterns. My experience in this project is to develop RTL code for internal IP blocks.

Tools & Lang: Xilinx ISE Design Suite & Verilog HDL.

2. Title: Implementation of 32-bit RISC Core using VHDL

Description:

The conventional RISC processors consume high power as compared with other processors. The power reduction in these processors is done in the fabrication step itself. But this is a complex process.We can implement the techniques for power reduction in front end process then we can easily design the low power processors without any complexity.

Tools & Lang: Xilinx ISE Design Suite, Modelsim & Verilog HDL.

Activities & Achievements:

Organized a technical paper presentation in CMR Engineering College (Avazya 2k13).

Presented a technical paper on “Optical Switching” at MRECW in 2K12.

Received awards for college Sports as part of Cricket and Volleyball team.

Personal Information:

Date of Birth

:

09-03-1993

Gender

:

Male

Father’s name

:

G. Rama Krishna

Mother’s name

:

G.Naga Jyothi

Permanent Address

:

H.No:8-381/1, New Manikya Nagar,

Suchitra (PO), Hyderabad-500067.

Declaration:

I hereby declare that the information given above is true to the best of my knowledge and belief.

(Gali Venkata Sai Ravi Teja)

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