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Product Development Design

Location:
Hyderabad, Telangana, India
Salary:
8LPA
Posted:
April 21, 2017
Email:
aczwwa@r.postjobfree.com

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B SAILU

*-*-***/**/***, Vinayak Nagar, SPR Hills, Yusufguda, Hyderabad-45 09666189825 aczwwa@r.postjobfree.com

VLSI PROFESSIONAL

Technically competent VLSI professional with M.Tech (Microelectronics and VLSI Design) from Indian Institute of Technology, Madras

Possess deep knowledge of Semiconductor Devices, Digital IC Design Techniques, CMOS circuit design and CMOS layout, RF IC Design ( LNA,PLL,PA, Phase Noise, gain, Mixer), Wiring issues, Timing issues in digital circuits, STA, RTL Circuit Design, Memory Design and Characterization, Digital Design Concepts & Digital system design using Verilog HDL design, Verilog HDL Simulation, Synthesis and Place & Route, Verilog RTL description of various designs, RTL Simulation, Synthesis and Place & Route.

Familiar with Synthesis techniques and Synthesis of Altera & Xilinx FPGA's.

Knowledge in CPLD/FPGA/SOPC/ ASIC Design Methodology & verification on test benches using Verilog HDL.

PV System Design and development according to project requirements and Simulate the project using PV Syst software.

Self motivated, hard working and goal-oriented with a high degree of flexibility, creativity, resourcefulness, commitment and optimism. An effective team player with outstanding communication and presentation skills

Technical Skills:

Operating Systems

Windows

Languages

C, Verilog HDL

Simulation & Synthesis

Modelsim, Synopsis (Sinplify), Xilinx Tool (Xilinx ISE), Altera Tool Synthesis (QUARTUS II)

Kits

SPARTAN-3E & Altera-DE2

BPM Tool

RSOFT

MATLAB

Simlink and Mathwork

PROFESSIONAL EXPERIENCE:

ORISSA POWER CONSORTIUM LTD, HYDERABAD May 2014 – Till Date

Dy. Manage

Design, Planning and Execution of MW range Solar PV Power Projects

Observance of Safety Rules & Guidelines, Leadership & Commitment to lead a Group of Employees

Prepare and submit complete DPR (Detailed Project Report), LOA, RFS and PPA.

Preparation of Reports to various sections of the Company, Implementation of Quality Systems, Coordination during Shutdown Activity to complete the jobs in time. Maintaining statutory compliances.

YMT TECHNOLOGIES, HYDERABAD Aug 2013 –May 2014

VLSI Trainer

Deliver proper Training on

PLD/FPGA/ASIC Design Methodology & Verification on test benches using Verilog HDL. FPGA Design, Simulate, Synthesis, Place and Route by using Xillinx Tools

RTL Design in Circuit Level & Verilog RTL Description of various designs, RTL Simulation, Synthesis and Place and Route

Digital IC design including NMOS/PMOS/CMOS Technologies, Fabrication of NMOS/PMOS/CMOS, Design with CMOS Gates, Characterization of CMOS Circuits, Scaling Effects, Parasitic Extraction, Layout Representation for CMOS Circuits, CMOS Fabrication Flows and Fundamentals, Timing Issues, Wiring Issues, Pipe line method for varies applications

MOSERBAER SOLAR LTD, DELHI. Jul 2011 – Feb 2013

Senior Engineer in Product Development

PV System Design and development according to project requirements and Simulate the project using PV Syst software.

Involve in requirement analysis, client interactions & meetings for understanding and freezing business requirements, preparing proof of concept, demos and presentations.

Designing, developing, testing, troubleshooting and debugging of the applications and managing smooth implementation and testing of the application at client location.

Developing product development cycle including development of embedded software and handling the development and maintenance of existing software and problem solving on the client-sites.

Designed & developed wireless PV (Photovoltaic) Data Loggers & Finalized specifications & identified vendors to develop required products.

PROJECTS

SOPC Design for Digital over Current Relay Aug’10 - May’11

M.Tech Project

Details:

FPGA (Field Programmable Gate Arrays) was used for the System on Chip (SOC) application to achieve a SOPC for the proposed design for distribution or sub-transmission networks.

The proposed relay followed standard inverse-time characteristics according to IEEE standard C37.112-1996.

Extensive use of Altera’s SOPC design development kit and CAD tools. The resultant output - SOPC builder configured a processor core in the form of a HDL file and then this file is used, together with HDL file of user-defined logic, for synthesis through standard CAD tool, Quatus II.

ACADEMIC & PROFESSIONAL CREDENTIALS

M.Tech,2011, Microelectronics and VLSI Design,

Indian Institute of Technology, Madras

Semiconductor Device Modeling Digital IC Design VLSI Technology Analog Circuits MOS Device Modeling

B.Tech, 2008, ECE (Electronics & Communication),

St Stanley College OF Engineering & Technology

Academic Accolades:

Acquired 254 Score in GATE’12

610 All India Rank with 613 Score in GATE’09

2220 All India Rank in GATE’07

Date of Birth: 15th March 1985 Languages: English, Telugu & Hindi References: Available on request.

B SAILU



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