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Engineering Design

Location:
Hyderabad, Telangana, India
Posted:
October 28, 2016

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Resume:

RAVITEJA PONUGUMATI

Mobile: 994-***-****.

Email: acw91v@r.postjobfree.com.

Professional Objective:

My objective is to work in a challenging environment which will bring the professional best out of me as well as contribute value to the organization. Educational qualification:

S.NO COURSE SCHOOL/COLLEGE/UNIVERSITY YEAR OF PASSING PERCENTILE 1.

M-Tech

(DECS) VISHNU INSTITUTE OF TECHNOLOGY 2017 77.5%

2. B-Tech QIS College of Engineering 2014 67.2%

(E.C.E) and Technology(JNTUK)

3. Polytechnic Bapatla Polytechnic College 2011 78.6%

(E.C.E) (JNTUK)

4. S.S.C Nirmal Vidhya Nikethan 2008 79%

Professional Qualification:

Maven Silicon Certified Advanced VLSI Design and Verification course (VLSI – RN): From: Maven Silicon VLSI Design and Training Centre, Bangalore. Year: August 2014.

Skills:

IT Skills

1. C-Language

2. Basics of JAVA

VLSI Domain Skills

HDL : Verilog

HVL : SystemVerilog

EDA Tool : Modelsim and ISE

Verification Methodologies : Coverage Driven Verification TB Methodology : UVM

Domain : ASIC/FPGA front-end Design and Verification Knowledge : RTL Coding, FSM based design, Simulation, Code Coverage, Functional Coverage, Synthesis.

Projects:

1) Title: FM Transmitter and Receiver

Team size: 6

Contribution: Analyze the operation of working of audio amplifier. Description: This is a small but quite powerful FM transmitter having three RF stages incorporating an audio preamplifier for better modulation. it has an output power of 4Watts and works off 12-18 VDC which makes it easily portable. 2) Title: A Vending Machine – RTL Design and Verification Team size: 3.

HDL: Verilog

HVL: SystemVerilog

EDA Tools: Modelsim, Questa -- Verification Platform and ISE Description: A vending machine is a machine. Which dispenses items such as snacks, lottery tickets, consumer products and even gold and gems to customers automatically, after the customer inserts currency or credit into the machine. 3) Title: Router 1x3 – RTL design and Verification Team size: 2.

HDL: Verilog

HVL: SystemVerilog

EDA Tools: Modelsim, Questa -- Verification Platform and ISE Description: The router accepts data packets on a single 8-bit port called data and routes the packets to one of the three output channels, channel-0, channel-1 and channel-2. Awards and achievements:

1) I got N.C.C. certificates ‘B’and’C’.

2) Participated in traffic control duties held in my N.C.C. periods. 3) Volunteered in Blood donation camps held at Bapatla College of Arts and Science. 4) Presented power point presentation about Smart Antenna Technology held at E.V.M College of Engineering and Technology.

5) Successfully organize technical festivals in the campus of QIS College of Engineering and Technology.

Personal profile:

Father’s name : P.Srinivasarao

Date of birth : 16-01-1993

Permanent address : 6-37,konijedu,tanguturu(M),prakasam(D),Andhra Pradesh, PIN-523272. Nationality : Indian.

Declarations:

I hereby declare that the above furnished details are true to the best of my knowledge.

( P.RAVITEJA)



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