| Resume alert | Resumes 41 - 50 of 136 |
Microsoft Office Engineering
Hyderabad, Telangana, India
... Chaitanya jr.college Vizag 2015 75% SSC Bhashayam Public School Vizag 2013 63% INTERNSHIPS: Internship on ‘VHDL Programming & its basic implementation on FPGA’S’ (DRDO) for a period of four weeks and have designed a project entitled ‘LED BLINKING’. ... - 2020 Feb 16
... Chaitanya jr.college Vizag 2015 75% SSC Bhashayam Public School Vizag 2013 63% INTERNSHIPS: Internship on ‘VHDL Programming & its basic implementation on FPGA’S’ (DRDO) for a period of four weeks and have designed a project entitled ‘LED BLINKING’. ... - 2020 Feb 16
Engineer Software
Hyderabad, Telangana, India
... ● Working experience on ARM Firmware and board bring-up & Board Support Packages (BSP) for custom boards designed based on Xilinx FPGA. ● Working experience in C with Data structures, Tcl and Shell scripting. ● Working experience on u-boot driver ... - 2020 Jan 08
... ● Working experience on ARM Firmware and board bring-up & Board Support Packages (BSP) for custom boards designed based on Xilinx FPGA. ● Working experience in C with Data structures, Tcl and Shell scripting. ● Working experience on u-boot driver ... - 2020 Jan 08
Sr. IT Recruiter/ Talent Acquisition/Sourcing/Payroll/HR
Hyderabad, Telangana, India
... Software Testing, Security Testing ERP’s : SAP, PeopleSoft, Oracle, BAAN Semiconductor/VLSI : ASIC Physical Design, ASIC Verification, Logic Design, RTL Design, DFT, SoC Design, SoC Verification, FPGA Design Verification, IP Verification, ... - 2020 Jan 06
... Software Testing, Security Testing ERP’s : SAP, PeopleSoft, Oracle, BAAN Semiconductor/VLSI : ASIC Physical Design, ASIC Verification, Logic Design, RTL Design, DFT, SoC Design, SoC Verification, FPGA Design Verification, IP Verification, ... - 2020 Jan 06
Design Data
Hyderabad, Telangana, India
... Verification, Assertion Driven Verification Tools : Cadence (NCSim & SimVision), IMC, Aldec Riviera Pro Domain : ASIC/FPGA front-end Design and Verification Knowledge : RTL Coding, FSM based Design, Coverage driven, Assertion based Verification ... - 2020 Jan 02
... Verification, Assertion Driven Verification Tools : Cadence (NCSim & SimVision), IMC, Aldec Riviera Pro Domain : ASIC/FPGA front-end Design and Verification Knowledge : RTL Coding, FSM based Design, Coverage driven, Assertion based Verification ... - 2020 Jan 02
Team Leader Power
Hyderabad, Telangana, India
... Title: SPACE VECTOR PWM CONTROL OF BLDC MOTOR Description: Theme of project is to implement space vector PWM technique using SPARTAN6LXT75 FPGA to control speed and position of a BLDC Motor in a Missile. Tools: MTALAB, XILINX, VHDL Program During B. ... - 2019 Dec 26
... Title: SPACE VECTOR PWM CONTROL OF BLDC MOTOR Description: Theme of project is to implement space vector PWM technique using SPARTAN6LXT75 FPGA to control speed and position of a BLDC Motor in a Missile. Tools: MTALAB, XILINX, VHDL Program During B. ... - 2019 Dec 26
Power Training
Hyderabad, Telangana, India
... languages C, C++, Core Java Assembly languages 8085,8086 and 8051 VLSI (VHDL coding to build Gates and FPGA for fabrication and Verilog) MATLAB (Simulink and coding) Training: Training on Embedded System at Technoking from July 2015 to August 2015. ... - 2019 Dec 11
... languages C, C++, Core Java Assembly languages 8085,8086 and 8051 VLSI (VHDL coding to build Gates and FPGA for fabrication and Verilog) MATLAB (Simulink and coding) Training: Training on Embedded System at Technoking from July 2015 to August 2015. ... - 2019 Dec 11
Engineering Project
Hyderabad, Telangana, India
... 2014 9.0 TECHNICAL SKILLS C STRENGTHS Good communication and Analytical skills Strategic and hardworking PROJECT A project on FPGA IMPLEMENTATION OF CARRY SAVE ADDER in VLSI from 06 june, 2018 to 05 july, 2018 HOBBIES Listening music Dancing Playing ... - 2019 Nov 15
... 2014 9.0 TECHNICAL SKILLS C STRENGTHS Good communication and Analytical skills Strategic and hardworking PROJECT A project on FPGA IMPLEMENTATION OF CARRY SAVE ADDER in VLSI from 06 june, 2018 to 05 july, 2018 HOBBIES Listening music Dancing Playing ... - 2019 Nov 15
Design Engineering
Hyderabad, Telangana, India
Durga KrishnaVeni.B Email: ac98kv@r.postjobfree.com SLV PG LADIES, Mobile:+91-918******* VijayaShree Layout,Hulimavu, LinkedIn ID:Krishnaveni-linkedin Bangalore, India – 560076 Summary of Qualifications • Good understanding of the ASIC and FPGA ... - 2019 Sep 02
Durga KrishnaVeni.B Email: ac98kv@r.postjobfree.com SLV PG LADIES, Mobile:+91-918******* VijayaShree Layout,Hulimavu, LinkedIn ID:Krishnaveni-linkedin Bangalore, India – 560076 Summary of Qualifications • Good understanding of the ASIC and FPGA ... - 2019 Sep 02
Technical Engineering
Hyderabad, Telangana, India
... 2012-13 8.3/10 Technical Skills Verilog and VHDL Arduino Programming SQL C++ Programming C Programming Digital Electronics Projects Designed Digital Alarm Clock using Field Programmable Gate Array (FPGA) with Verilog Hardware Description Language. ... - 2019 Aug 24
... 2012-13 8.3/10 Technical Skills Verilog and VHDL Arduino Programming SQL C++ Programming C Programming Digital Electronics Projects Designed Digital Alarm Clock using Field Programmable Gate Array (FPGA) with Verilog Hardware Description Language. ... - 2019 Aug 24
Soldering technition Test eq. network analyzer, Spectrum analyzer, Si
Hyderabad, Telangana, India
... • Soldering of multilayer PCBS worked in Leaded Components, SMDs, CPLDS, FPGA,BUFFERS and DDC etc. • Hi-Reliable soldering work done in leaded, SMDS components & DE-Soldering. • Crimping of wires 16 -28 SWG wires worked • RF Semi-rigid cables work ... - 2019 Aug 23
... • Soldering of multilayer PCBS worked in Leaded Components, SMDs, CPLDS, FPGA,BUFFERS and DDC etc. • Hi-Reliable soldering work done in leaded, SMDS components & DE-Soldering. • Crimping of wires 16 -28 SWG wires worked • RF Semi-rigid cables work ... - 2019 Aug 23