| Resume alert | Resumes 61 - 70 of 161 |
Engineer Design
Chennai, TN, India
... KEY PROJECT DETAIL Project Name Nallatech (NX0503_385A) Description This is the 385A-SoC System on Chip FPGA Accelerator Card 16 layers with the size of 6.5”X3" Total Number of Components: 1002 Altera Arria 10 SX F34 package Main Processor BGA with ... - 2018 Jan 03
... KEY PROJECT DETAIL Project Name Nallatech (NX0503_385A) Description This is the 385A-SoC System on Chip FPGA Accelerator Card 16 layers with the size of 6.5”X3" Total Number of Components: 1002 Altera Arria 10 SX F34 package Main Processor BGA with ... - 2018 Jan 03
Sales Executive Engineering
Chennai, TN, India
... Attended One Day Workshop on ADVANCED ETHICAL HACKING at Systech Hardware and Networking Academy on 9.3.2013 Attended One Day Workshop on “FPGA and VLSI Design” at kings college of engineering,Tanjore conducted by MYCIRCUITS, HOSUR. Attended ... - 2017 Dec 11
... Attended One Day Workshop on ADVANCED ETHICAL HACKING at Systech Hardware and Networking Academy on 9.3.2013 Attended One Day Workshop on “FPGA and VLSI Design” at kings college of engineering,Tanjore conducted by MYCIRCUITS, HOSUR. Attended ... - 2017 Dec 11
Project Electrical Engineering
Chennai, TN, India
... Academic Projects Project Title : Implementation of VLSI based gray level morphology with FPGA Organization : Micro Track Industries Platform used : Xilinx Platform studio Contribution : To Detect the Block Diagram details & explain it Description : ... - 2017 Nov 21
... Academic Projects Project Title : Implementation of VLSI based gray level morphology with FPGA Organization : Micro Track Industries Platform used : Xilinx Platform studio Contribution : To Detect the Block Diagram details & explain it Description : ... - 2017 Nov 21
Engineering Design
Chennai, TN, India
... FPGA Tools - Mentor Graphics, Altera, Xilinx. Design Tools - Cadence tools, Leonardo spectrum, Tanner tools. Simulators - Tanner EDA. Layout editors - Virtuoso (Cadence), Tanner. AREA OF INTEREST: Research Interest Research interest Teaching ... - 2017 Oct 17
... FPGA Tools - Mentor Graphics, Altera, Xilinx. Design Tools - Cadence tools, Leonardo spectrum, Tanner tools. Simulators - Tanner EDA. Layout editors - Virtuoso (Cadence), Tanner. AREA OF INTEREST: Research Interest Research interest Teaching ... - 2017 Oct 17
Looking Forward For The Job As Asic Design/Verification Engineer
Chennai, TN, India
... driven & Assertion based Verification TB Methodology : UVM Protocol : SPI and AMBA EDA Tool : Questasim and ISE Domain : ASIC/FPGA front-end Design and Verification Knowledge : RTL Coding, FSM based design, Simulation, Code Coverage, Functional ... - 2017 Oct 16
... driven & Assertion based Verification TB Methodology : UVM Protocol : SPI and AMBA EDA Tool : Questasim and ISE Domain : ASIC/FPGA front-end Design and Verification Knowledge : RTL Coding, FSM based design, Simulation, Code Coverage, Functional ... - 2017 Oct 16
Design Engineer Engineering
Chennai, TN, India
... Project: VLSI Implementation of Memory Efficient 2-D FIR Filter using RDA Technique Programming Language: VHDL Kit: Altera FPGA kit Description: The memory Efficient 2-D FIR filter structure is designed to provide wide applications in many cost ... - 2017 Oct 16
... Project: VLSI Implementation of Memory Efficient 2-D FIR Filter using RDA Technique Programming Language: VHDL Kit: Altera FPGA kit Description: The memory Efficient 2-D FIR filter structure is designed to provide wide applications in many cost ... - 2017 Oct 16
Engineer Design
Chennai, TN, India
R Kumaran Design engineer ac2pvy@r.postjobfree.com 720******* SUMMARY M.tech with 2.3 Years of experience in FPGA Design Engineer. Worked on module architec- ture design, RTL coding and simulation. Worked on synthesis and implementation. Experience ... - 2017 Oct 11
R Kumaran Design engineer ac2pvy@r.postjobfree.com 720******* SUMMARY M.tech with 2.3 Years of experience in FPGA Design Engineer. Worked on module architec- ture design, RTL coding and simulation. Worked on synthesis and implementation. Experience ... - 2017 Oct 11
Engineering Service
Kelambakkam, TN, India
... EDUCATION 2010-2012 MASTER OF ENGINEERING SMK FOMRA INSTITUTE OF TECHNOLOGY, CHENNAI ANNAUNIVERSITY CHENNAI CGPA-7.2 OVERVIEW OF MY THESIS:DESIGN AND IMPLEMENTATION OF ERROR DETECTION AND CORRECTION USING FPGA 2009-2011 MBA (H.R) PERCENTAGE-64.12% ... - 2017 Oct 05
... EDUCATION 2010-2012 MASTER OF ENGINEERING SMK FOMRA INSTITUTE OF TECHNOLOGY, CHENNAI ANNAUNIVERSITY CHENNAI CGPA-7.2 OVERVIEW OF MY THESIS:DESIGN AND IMPLEMENTATION OF ERROR DETECTION AND CORRECTION USING FPGA 2009-2011 MBA (H.R) PERCENTAGE-64.12% ... - 2017 Oct 05
Software validation engineer with 3+ years experience
Chennai, TN, India
... SVN Version control tool Knowledge on Visual Studio 2010 Defects Reporting tool (Mantis) FPGA Flashing tool (Xilinx Debugger) Open office, Microsoft office Operating Systems : Windows, Linux Language : Basics of C, Perl and Batch Scripting ... - 2017 Sep 20
... SVN Version control tool Knowledge on Visual Studio 2010 Defects Reporting tool (Mantis) FPGA Flashing tool (Xilinx Debugger) Open office, Microsoft office Operating Systems : Windows, Linux Language : Basics of C, Perl and Batch Scripting ... - 2017 Sep 20
Engineering Project
Chennai, TN, India
... WORKSHOP & IPT ATTENDED: WORKSHOP ON CONDUCTED BY PERIOD FPGA firmware development in VLSI GENN CONTROLS OF INDIA PRIVATE LIMITED 1 Day Fundamentals of telecom BSNL (a govt. of india enterprise) 5 Day EXTRA CURRICULAR ACTIVITIES : • Active Player of ... - 2017 Sep 14
... WORKSHOP & IPT ATTENDED: WORKSHOP ON CONDUCTED BY PERIOD FPGA firmware development in VLSI GENN CONTROLS OF INDIA PRIVATE LIMITED 1 Day Fundamentals of telecom BSNL (a govt. of india enterprise) 5 Day EXTRA CURRICULAR ACTIVITIES : • Active Player of ... - 2017 Sep 14