Design Engineer Engineering
Resume:
PUNITHA P G
Ranipet,
Vellore District- 632401
Contact: +91-979*******, 812-***-****
Email: **************@*****.***
Ability to think innovatively and capable of involving in Research activities in the growing field of VLSI and its application areas.
Summary
Good Working knowledge of Xilinx, Modelsim .
Have hands on experience in Cadence Nc launch (Digital Design) and Virtuoso (Analog Design)
Have knowledge of designing Analog,Digital Circuits.
Good knowledge in Digital electronics
Good understanding of VLSI system design and have a sound knowledge in its underlying concepts .
Basic knowledge in system Verilog assertions, verification methodologies such as UVM, OVM.
Technical Expertise
Languages: Verilog, VHDL.
OS: Windows, LINUX
IDE: Matlab(12.0a).
System Verilog, System Verilog Assertions and UVM
Basic Knowledge in PERL
Allegro Capture, Pspice, PCB Editor
Experience: Working as an Assistant Professor in Sri Chundi Ranganayakulu Engineering College, Guntur for the duration of 1 year 6 months.
Project: VLSI Implementation of Memory Efficient 2-D FIR Filter using RDA Technique
Programming Language: VHDL
Kit: Altera FPGA kit
Description:
The memory Efficient 2-D FIR filter structure is designed to provide wide applications in many cost effective medical imaging techniques.
Memory footprint of 2-D FIR filter gets reduced by using two techniques such as Memory Reuse and memory Sharing .
The main principle behind memory reuse is (block based processing) a new architecture is developed which processes block of inputs simultaneously eventually uses lower memory bandwidth.
Due to this memory footprint gets reduced, which ultimately achieves the improvement in key metrics of VLSI such as area, speed and power.
The MAC unit in the block based architecture gets replaced by Reusable Distributed Arithmetic Architecture.
This replaced structure further provides the advantage of linear memory dependence which inturn greatly optimises the system.
Project: Spectral Entropy Based Voice Activity Detection Using Spectral Subtraction Filter and TEO Filter.
Programming Language: Matlab
Tools: DSP Processor Kit
Description:
To separate the clean speech from several kind of noises which affects the characteristics of voice signal.
Removal of Noise is done by two newly designed filters such as Spectral Subtraction and Teager Energy Operator Filter.
The Clean speech is analysed based on the response of the filter outputs characteristics.It depends on its Spectral Entropy and colour characterization.
By using these newly derived filter designs minute voice activities can also be detected .
Leadership Skill
Performed as a Chief Secretary of overall college departments and certified by Dean as a best secretary in my college records.
Academic Records
First Class in M.E. - VLSI DESIGN in Saveetha Engineering College under Anna University,Chennai with CGPA of 8.03
First Class in under graduation (B.E. Electronics and Communication Engineering), in University College of Engineering Villupuram,( a constituent college of Anna University Chennai ) with (CGPA of 8.11) in the year on April 2013.
HSC from Vitva Ratna Villa Girls Higher secondary school with distinction of 91.75% in board examinations held in March 2009.
SSLC from Vitva Ratna Villa Girls Higher secondary school with distinction of 92.4% in board examinations held in April 2007.
Recorded the scores of HSC and SSLC as a school Topper and Third Topper in that respective year.
RESEARCH PAPER
1.P. G. Punitha, R. Ramesh, Review of Memory Efficient 2-D Finite Impulse Response (FIR) Filter Architecture, Middle East Journal for Scientific Research, Vol: 23, No:5, ISSN: 1990-9233, pp: 957-961 .
Personal Information
Father s Name : P.Gajapathi
Nationality : Indian
Language : Tamil (proficient), English (proficient),Telugu(Speak)
Address : No 18 A/2,Godown Street,Ranipet,Vellore-632401
Place : Ranipet
Dated : P.G.Punitha
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