VINOTH RAVINDRAN

E-Mail: ac3vyj@r.postjobfree.com

Mobile: +91-948*******, +918*********

Career Objective: Seeking assignments and PCB Layout Design Engineer with a technology oriented organization that gives scope to involve my knowledge and skills for design,

Testing and development and be a part of a team that dynamically works

Towards the growth of organization.

EDUCATIONAL QUALIFICATIONS

Diploma in EEE April - 2009

Thanthai Periyar Polytechnic College, Vellore

PCB Design Relevant Experience 6 Years. Overall Experience – 7.7 Months

Embdes Technologies, Chennai May 2017 to Till Now.

Role: Senior PCB Engineer

(High Speed PCB Design, Mixed Signals PCB Design, Component Selection & Procurement, Component Library Creation, Gerber Final Verification & Release)

Medontech Pvt Ltd, Chennai, Tamilnadu June 2016 to April 2017.

(Component Library Creation, PCB Designing, Board Conversion, Gerber Verification & Analysis)

Schlumberger Pvt. Ltd., Pune, Maharashtra Apr 2013 to May 2016

Role: ECAD (Electrical CAD) – Designer

(PCB Design, Library Creation, Component RoHS and BOM Validation, Wire Harness Design, Test Equipment Design, Product Life Cycle Management)

Embdes Technologies Pvt Ltd, Bangalore Mar 2012 to March 2013

Role: PCB Designer

(High Speed PCB Design, Library Creation and Management)

VVDN Technologies Pvt Ltd, Gurgaon Mar 2010 to Mar 2012

Role: DFT Designer (PCB Testing, Wire Harness, ATE Boards Design, etc.)

LUCAS TVS, Chennai September 2009 to March 2010.

Role: Production Trainee

SKILL SET: EDA TOOLS

PCB DESIGN TOOL

Cadence Allegro (16.6)

Altium Designer 16

SCHEMATIC TOOL

OrCAD Capture CIS,

Concept HDL

Altium Designer 16.1

GERBER ANALIZE TOOL

CAM 350, View mate

Symbol / Library Creation

OrCAD, Concept HDL / Allegro 16.5, Altium 16/ Pads

EXPERIENCE SUMMARY

Schematic Design, aware about the Polarized Components & Effective Utility of Heterogeneous part,

Trouble shoots error and Net-list Extraction

PCB Parts Library Creation

Critical Components Placement with proper guideline standard

Take care of DFA and DFM

Take care of EMI and EMC

Take care to maintain Signal Integrity

Knowledge of Impedance Matching based on the Layer Stack-Up Structure

Aware about Signal Parallelism

Better Plan to run Critical Signals with separate & shielded Ground-Reference

Maintain the Balanced Copper density in each individual layer

Advanced knowledge of constraints set

Expertise in usage of Blind & Buried vias

Experience in RF PCB component placement and routing, coplanar, ground shielding techniques.

HIGHLIGHTS

Ability to fix Board Size, Number of Layers and Layer Stack-up Structure, based on the available critical Fan-out Parts and total count of components

Experienced in analog, digital, RF and mixed signal circuit design

Expertise in Signal Grouping, Pin-Pair settings & Length Matching for DDR Memory Slot

Experience in Reverse Engineering to extract Layout from Gerber Files through CAM Static in Altium, Allegro.

Experience in Gerber Analyze & Net-list compare and Analyze in CAM 350

Tool Conversion Boards from DXF, Gerber to Complete Matched Outputs.

KEY PROJECT DETAIL

Project Name

Nallatech (NX0503_385A)

Description

This is the 385A-SoC System on Chip FPGA Accelerator Card

16 layers with the size of 6.5”X3"

Total Number of Components: 1002

Altera Arria 10 SX F34 package

Main Processor BGA with 1152 pins

2 Banks 4G DDR4 SDRAM

8-Lane PCI-Express Gen 3

Challenges, Technologies used

39.37 mils pitch BGA Fan-out and Trace Out all signals in 8 Layers

Length matching the DDR4 in Daisy Chain topology routing method for Address lines

Narrow edge routing path to avoid stub, Proper Shield to avoid noise

DDR4 Interface Routings, PCIe Express Interface

Role & Contribution

Creating Board Outline with Mechanical Spec, Placement Confirmation, Power Splitting, Lane Grouping & Length Matching

Tools & Gerber Verification

Altium Designer 16.1 & CAM350

Project Name

DIGITAL FFT SPECTROMETER

Description

A/D Converter

Number of Layers 14

243 Main controller BGA with 39.37 mils pitch

Number of Relays controlled by common Clock Signal

Challenges, Technologies used

High consideration of Grouping and Overcome the Placement restriction

to separate Analog & Digital components

More EMI and EMC consideration to maintain Signal Integrity

Better Planning for Power & Ground split with high spacing constraint

Clock Signal Routed with Star Topology and length matched

Role & Contribution

Provide independent Design flow for Analog & Digital Signals

throughout the layout

Tools

Altium Designer 2016

Project Name

Road Runner

Description

This is the card for intelligent transportation system (ITS)

10 layers with the size of 7”X4.5”

Total Number of components 858

Main Processor BGA with 516 pins;

4x256MB DDR4 with miniPCI

Challenges, Technologies used

High Density Board with Critical Placement Constraint

Blind & Buried vias used to Fan-Out 19.69 pitch BGA

DDR2 Length Matched in T-Topology Routing style & miniPCI routed in Daisy chain Topology

Back Drill provided to avoid Signal Dangling

Role & Contribution

Components placement, routing, length matching

Length Mach report added

Back Drill Specification added in Fabrication-Layer

Tools

Alitum Designer16

Project Name

ATE Boards

Description & Technologies used

Automated Test Equipment PCB to Test Production IC

Number of Layers 32 Circle Board

2808 Pin BGA was sounded by 25 Test Channels

BGA Pins divided by Number of Poles & Each Pole carries specific Pole Supply

Role & Contribution

Best Fit Routing, Force & Sense Routing

Allocating CAP-STRIP to place Stacked Capacitors for filtering

Power Sense and Ground Sense signal routing for individual Power Split

Back annotate the Schematic to match with Best Fit routing in Layout

Tools

Altium Designer 16

Project Name

Reverse Engineering

Description & Technologies used

Extract the PCB from Gerber files through CAM 350 and convert into Altium or Allegro Tool Sets.

Role & Contribution

Gerber Data for Electrical & Silkscreen Layers - Mandatary

Drill File - Optional (If it not available, we can Export from CAM )

Pick & Place Data - Optional (If it available, we CAM - Exported from PCB)

Net-list - Optional (Just to Replace the Tool Generated Net-list)

Role & Contribution

Export the PCB by CAM static in Altium – Consists of Free Pads

Create the Footprint by Grouping the Free Pads & Silkscreen

Place the Created Symbols with respective coordinates by Pick & Place Data

Import the Original Netlist to Replace the Tool Generated Netlist PCB

Tools

Altium

PERSONAL DETAILS

Father’s Name : Ravindran

Date of Birth : 04-December-1987

Nationality : Indian

Languages Proficiency : English, Tamil

Marital Status : Single

Passport Number : H9112433

Permanent Address : 2/1, Kuppuswamy St, Chengalpattu, Kancheepuram dt.

Pin – 603002

DECLARATION

Hereby I declare that the above furnished details are true to the best of my knowledge.

Place : Chennai Signature

Contact this candidate