Engineering Design

M.SENTHIL SIVAKUMAR

E_Mail: *****************@*****.***

Mobile: 91-938*******

Chrompet, Chennai-44

CAREER OBJECTIVE:

To obtain a position as an engineer/researcher in the areas of microelectronics/IC design technology and low power VLSI design.

WORKING EXPERIENCE:

1. Research Scholar at MIT Campus-Anna university Chennai – Jun 2014 – Till date

2. Assistant Professor at NIT Puducherry, Karaikal, India – Jan 2014 to May 2014.

3. Lecturer at St. Joseph University in Tanzania, East Africa – Sept 2009 to Oct 2013.

4. Lecturer at Gojan School of Business and Technology, Chennai, India – Aug 2005 to Jun 2007.

ACADEMIC QUALIFICATION:

Doctor of Philosophy (PhD) –Pursuing

MIT Campus-Anna University, Chennai, India (From June 2014)

(DST Purse-II Fellow from Jan-2015-Mar-2016) (UGC-RGNF-JRF Fellow from Apr-2016-Till Date)

Master of Technology in VLSI design, CGPA-7.43/10.

Vellore Institute of Technology, VIT University, Vellore, India - (2007-2009).

• Thesis: “High-Performance Low-Power FFT Cores”

Bachelor of Engineering in Electronics and Communication, 71.2%. Oxford Engineering College, Anna university, Chennai, India - (2001-2005)

• Project: “Automatic Unmanned Railway Using WAP”

Higher Secondary (2000-2001) - Percentage-72.83%

Secondary (1998-1999) - Percentage-83.6%

Baren Bruck Higher Secondary School, Tirunelveli, Tamilnadu.

SKILLS:

Languages - C, Verilog HDL, System Verilog, MAT lab.

FPGA Tools - Mentor Graphics, Altera, Xilinx.

Design Tools - Cadence tools, Leonardo spectrum, Tanner tools.

Simulators - Tanner EDA.

Layout editors - Virtuoso (Cadence), Tanner.

AREA OF INTEREST:

Research Interest

Research interest

Teaching interest

ASIC Design,

CMOS VLSI Design

Analog and Digital IC Design,

Microprocessor,

Digital signal processing and system design,

Analog and Digital Integrated circuits.

Microprocessor,

Digital signal processing,

Digital system design,

AWARDS WON:

1.Best Paper Award - NCIETET'15 (National Conference in Innovative & Emerging Trends in Engineering and Technology, 2015), Chennai.

2.Best Student Project award in, “CADENCE DESIGN INDIA CONTEST 2009”, Bangalore, India.

Project: Design of Dynamically Reconfigurable Fully Optimized Low Power FFT/IFFT Architecture for MC-CDMA Receiver.

3.Best Student Project award in, “INTEL INDIA SCHOLARSHIP PROGRAM 2008”, Bangalore, India.

Project: Low Power CMOS Dynamic Logic for Arithmetic Circuits with High Speed.

PUBLICATIONS:

TEXT BOOKS:

1.Fundamentals of DIGITAL DESIGN- Published by S.Chand publishers, ISBN: 978-93-84319-12-0.

2.Linear Integrated circuit -Published by S.Chand publishers, ISBN: 978-81-219-4113-6.

RESEARCH PAPERS: Journals:

M. Senthil Sivakumar, S. P. Joy Vasantha Rani, “Area Efficient digital Built-In Self-Test for Analog to Digital Converter”, International journal of electronics

Senthil Sivakumar M, Gurumekala T, Sundaram A, Thandaiah R, Arputharaj T, "Design of low power FFT processors using Multiplierless Architecture", ARPN Journal of Engineering and Applied Sciences (Annexure II)(Thomson Reuters & Scopus indexed)- Vol. 10, No. 11, June 2015, ISSN 1819-6608, pp.4937-4941.

Senthil Sivakumar M, Gurumekala T, Sundaram A, Banupriya M and Arputharaj T, “Design of Novel AES processor for High Speed Next Generation Internet Security”, International Journal of Applied Engineering Research(IJAER)(Annexure II) (Scopus indexed)-Vol.10, Issue No 55, 2015, pp.389-393.

Gurumekala T, Senthil Sivakumar M, Sundaram A and Arputharaj T, “Enhanced Fuzzy Based Clustering Approach for Improving Reliability of WSNs”, International Journal of Applied Engineering Research (IJAER), (Annexure II) (Scopus indexed)- Vol.10, Issue No 55, 2015, pp.1314-1319.

Gurumekala T, Senthil Sivakumar M, Sundaram A and Arputharaj T, “Identification of High Throughput Path in WMNs using Novel Routing Metric”, International Journal of Applied Engineering Research (IJAER), (Annexure II) (Scopus indexed)- Vol.10, Issue No 55, 2015, pp.1278-1283.

Senthil Sivakumar M, Sundaram A, Gurumekala T and Banupriya M, “Design of ALU using reversible logic based Low Power Vedic Multiplier”, IJSER (Indexed by Thomson Reuters), vol.6, issue 2, Feb 2015, pp.5-8.

Senthil Sivakumar M, S.A.Jayadhas, Arputharaj T, and Banupriya M “Design of Dynamically Reconfigurable Adaptive MC-CDMA Receiver using FFT Architecture”, African Journal of Information and Communication Technology (AJICT) 2013, Vol.7, No.2, pp.49-61.

Senthil Sivakumar M, Arockia Jayadhas S, Arputharaj T, and Banupriya M “Design of 4-Bit Manchester Carry Look-Ahead Adder Using MT-CMOS Domino Logic”, African Journal of Information and Communication Technology (AJICT) 2013, Vol.7, No.2, pp.62-72.

Senthil Sivakumar M, Arockia Jayadhas S, Arputharaj T, and Banupriya M, “Low Noise Active Integrated Antenna for S-Band”, African Journal of Information and Communication Technology (AJICT) 2013, Vol.7, No.2, 2013, pp.37-48.

Senthil Sivakumar M, Banupriya M, Arockia Jayadhas S, Arputharaj T, “Speech Controlled Automatic Wheelchair for Home Navigation System”, International Journal of Machine to Machine Communication (JMMC), River Publishers Denmark.

Senthil Sivakumar M, Arockia Jayadhas S, Arputharaj T, and Ramkumar E, “Design of MT- CMOS Domino Logic for Ultra Low Power High Performance Ripple Carry Adder”, IJESC, vol.5, No.1, Jan-Jun, 2013, pp.37-40.

Senthil Sivakumar M, S.A.Jayadhas, Arputharaj T, and Ramkumar E, “Design of MT-CMOS Domino Logic for Ultra Low Power High Performance RCA”, International Journal of Emerging Trends in Engineering and Development (IJETED), 2013, vol.1, iss.3, pp.574-579.

Senthil Sivakumar M, Banupriya M, “Low power high performance design consideration of CMOS domino logic for fast adders”, Journal of Scientific Theory and Methods, 2012, vol.12, pp.22-39.

Senthil Sivakumar M, Banupriya M, Arockia Jayadhas S, “Design of Low Power High Performance 16-Point 2-Parallel Pipelined FFT Architecture”, IJECIERD, Sept 2012, vol.2, issue.3, pp.12-26.

Senthil Sivakumar M, Banupriya M, “Design Consideration of Dual Threshold Logic for High Performance and Ultralow Power Carry Look-Ahead Adder”, IJSER (Indexed by Thomson Reuters), vol.3, issue 6, June 2012, pp.1301-1306.

Senthil Sivakumar M, Banupriya M, “High Speed Low Power Flash ADC Design for Ultra Wide Band Applications”, IJSER (Indexed by Thomson Reuters), vol.3, issue 5, May 2012, pp.389-393.

Conference and Symposium:

Ashwini S, M. Senthil Sivakumar, S. P. Joy Vasantha Rani, “Design of Linear Ramp Generator for ADC”, proc.of IEEE 4th International Conference on Signal Processing (2017), Communications and Networking, MIT-Anna University, Chennai-600044.

M. Senthil Sivakumar, S. P. Joy Vasantha Rani, “Design of digital Built-In Self-Test for Analog to Digital Converter”, proc.of IEEE 10th International Conference on Intelligent Systems and Control (ISCO 2016), vol.2, pp.1-6, DOI: 10.1109/ISCO.2016.7727134.

M. Senthil Sivakumar, S. P. Joy Vasantha Rani, “A Review on Built-In Self-Test of Analog to Digital Converter”, proc.of 2015 Online International Conference on Green Engineering and Technologies (IC-GET), vol.2, pp.198-204.

Sundaram A1, SenthilSivakumar M2, G.G.Weldearegai and Dawit A, “Power Quality Improvement of Electric Grid Connected Wind–Solar Hybrid Energy System using STATCOM”, proc.of First International Conference on Recent Trends in Engineering and Technology-(FICRTET15), Organized by Ambo university, Ethiopia, NIT, Trichy, Georgia institute of technology, USA.

Senthil Sivakumar M, Gurumekala T, Sundaram A, Thandaiah R, Arputharaj T, "Design of low power FFT processors using Multiplierless Architecture", proc. of NCIETET'15, Panimalar Institute of Technology, Chennai, May 14th 2015,pp.53-56 (Won Best Paper Award).

Senthil Sivakumar M, Gurumekala T, Sundaram A, Banupriya M and Arputharaj T, “Design of Novel AES processor for High Speed Next Generation Internet Security”, proc. of ICAAET – 2015, May 14th -16th 2015, pp.1448-1451.

Gurumekala T, Senthil Sivakumar M, Sundaram A and Arputharaj T, “Enhanced Fuzzy Based Clustering Approach for Improving Reliability of WSNs”, proc. of ICAAET – 2015, May 14th -16th 2015, pp.942-946.

Gurumekala T, Senthil Sivakumar M, Sundaram A and Arputharaj T, “Identification of High Throughput Path in WMNs using Novel Routing Metric”, proc. of ICAAET – 2015, May 14th -16th 2015, pp.774-778.

M. Senthil Sivakumar, R. Thandaiah Prabu and I. Jayanandan, “Design of Digital Clock Calendar Using FPGA”, IETE 45th Mid-term Symposium on Broadband Technologies and Services for Rural India, 4th and 5th April, proceeding of CIIT’2014.

Senthil Sivakumar M, Arockia Jayadhas S, Arputharaj T, and Banupriya M, “4-Bit Manchester Carry Look-Ahead Adder Design Using MT-CMOS Domino Logic”, proc. of IEEE Pan African International conference on PACT, July 2013, pp.15-18.

Senthil Sivakumar M, Arockia Jayadhas S, Arputharaj T, and Banupriya M, “Design of Adaptive MC-CDMA receiver using low power parallel-pipelined FFT architecture”, proc. of IEEE Pan African International conference on PACT, July 2013, pp.29-33.

Arputharaj T, Senthil Sivakumar M, Arockia Jayadhas S, and Banupriya M, “Design of Low Noise Active Integrated Antenna”, proc. of IEEE Pan African International conference on PACT, July 2013, pp.66-69,

Senthil Sivakumar M, Banupriya M, Jaykishan Murji, Lightness D Jacob, and Frank Nyange, “Speech Controlled Automatic Wheelchair”, proc. of IEEE Pan African International conference on PACT July 2013, pp.70-73.

Senthil Sivakumar M, Arivu Selvam, and Banupriya M, “Design of 4-Bit Carry Look-Ahead Adder Using MT-CMOS Dynamic Logic” proceeding of International Conference on Electrical Sciences (ICES - 2012), Sastra University, India, 2012, page-42.

M.Senthil Sivakumar, Jhonson G, “Fast Adders Using High performance low power CMOS dynamic logic” proceeding of International Conference on Active /Smart Materials (ICASM), 2009, Thiagarajar College of Engineering, Madurai, India.

M.Senthil Sivakumar, Rakesh Kumar, and L.Thanga Durai, “High performance Carbon Nano Tube (CNT)-Field Effect Transistor”, proceeding of International Conference on Active /Smart Materials (ICASM), 2009, Thiagarajar College of Engineering, Madurai, India.

Reviewer In:

1.IEEE International Conference on Computing Methodologies and Communication (ICCMC 2018), India

2.9th International Conference on Computational Intelligence and Communication Networks 2017, Final International University, Cyprus.

3.Fifth ediiton of International Conference on Advances in Computing, Communications and Informatics ICACCI-2016, Jaipur, India.

4.Third International Symposium on Intelligent Systems Technologies and Applications (ISTA'17), 2016, Manipal, India.

5.GSCIT' 2014 (International Conference on Education & eLearning Innovations ICEELI’14), 2014 in Sousse, Tunisia.

6.3rd International conference on Advances in computing, communication and Informatics, 2014, Galgotias College of Engineering & Technology, Greater Noida, India.

7.Third International Symposium on Intelligent Distributed Computing, 2014, Galgotias College of Engineering & Technology, Greater Noida, India.

8.Third International Symposium on Intelligent Informatics (ISI’14), 2014, Galgotias College of Engineering & Technology, Greater Noida, India.

9.ICSPCT 2014 (International Conference on Signal Propagation and Computer Technology 2014), July 2014, Govt. Engineering College Ajmer, India. www.edas.info.

10.Pan African Conference for Information Science, Computing and Telecommunications, 2014, Arusha, Tanzania, East Africa. www.edas.info.

11.International Journal of Electronics from 2011.

PARTICIPANT in WORKSHOPS/CONFERENCES:

1.1st International Test Conference India (ITC India), Bangalore, India, through ITC Fellowship.

2.Editorial Workshop on "How to Publish with Taylor & Francis" (05-08-2016), organized by Anna University Library, Chennai-25.

3.Springer Author Workshop, College of Engineering, Guindy, Anna University, Chennai, India.

4.Two-day national workshop on VLSI design verification and testing (18-03-2016 to 19-03-2016), organized by School of Electronics Engineering, VIT University, Vellore, India.

5.“Competence Based Curriculum Development”, St.Joseph College of Engineering and Technology, Dar-Es-Salaam, Tanzania, East Africa.

LEADERSHIP:

1.Teaching assistant in two week ISTE STTP on CMOS, Mixed Signal and Radio Frequency VLSI Design organized by IIT, Kharagpur under National Mission on Education through ICT (MHRD).

2.TARANGG’14 Workshop on 1.Arduino Robotics, and 2.Routing all the way, NITpy, Karaikal.

2. Technical Project Exhibition “Techfest”, SJUIT, Tanzania 2010.

3. Short term course on “Real time Embedded system and VLSI design”, SJUIT, Tanzania 2010.

REFERENCE:

1. Dr.Joy Vasantha Rani S P, Assistant Professor (Sr.Gr), MIT Campus - Anna University, Chennai.

2. Prof Sakthivel.R, Asst.Professor (Sr.Gr), VLSI division, VIT University, Vellore.

3. Mr.Ranjith.A, Asst.Professor, St. Joseph University in Tanzania, East Africa.

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