Looking Forward For The Job As Asic Design/Verification Engineer
Resume:
RESUME
KALPANA RAJAN
Bhagyalakshmi pg, #GA
*nd Cross Road, G K Govinda
Reddy Layout,Opposite
Arekere
Bangalore - 560076
Phone No: +91-
e-Mail : **************@*****.***
Career Objective
To work in an appropriate position in VLSI front end field, which will enrich and utilize my technical as well as experience knowledge and where I can enhance skills and knowledge through continuous learning thereby put whole effort towards burgeon for the company and myself.
Summary of Work Experience
Currently, Intern at Maven Silicon Softech Pvt Ltd, Bangalore.
Embedded Developer in Code Bind Technologies (Oct’ 2014 – Oct’ 2015).
Project Assistant in Dr.Dharmambal Govt. Polytechnic College (Nov’ 2011 – Apr’ 2012 ).
Educational Qualifications
Year Institute/University Degree/Examination Percentage 2017 Maven Silicon Advanced VLSI Design
and Verification Completed
Course
2014 SreeSastha Institue Of Engineering M.E CGPA-7.3 and Technology (in VLSI Design)
2011 SSN College of Engineering B.E in ECE) 70.00
2008 Dr. Dharmambal Govt.
Polytechnic College for Women
Diploma in ECE 94.5
2005 Gnanodhaya Girls High School SSLC 89.6
Summary of Project Experience
VLSI Projects
[1] Router 1x3 – RTL design and Verification
HDL: Verilog
HVL: System Verilog
TB Methodology: UVM
EDA Tools: Questasim and ISE
Description: The router accepts data packets on a single 8-bit port and routes them to one of the three output channels, channel0, channel1 and channel2. Responsibilities:
Architected the design and Implemented RTL using Verilog HDL.
Architected the class based verification environment using system Verilog
Verified the RTL model using SystemVerilog.
Generated functional and code coverage for the RTL verification sign-off
Synthesized the design
[2] SPI Controller Core - Verification
HVL: SystemVerilog
TB Methodology: UVM
EDA Tools: Questasim
Description: The SPI IP core provides serial communication capabilities with external device of variable length of transfer word. This core can be configured to connect with 32 slaves. Responsibilities:
o Architected the class based verification environment in UVM o Verified the RTL module using System Verilog and generated functional and code coverage for the RTL verification sign-off
[3] AHB2APB Bridge IP Core Design
HDL: System Verilog
EDA Tool: Questasim
Description: The AHB to APB bridge is an AHB slave which works as an interface between the high speed AHB and the low performance APB buses
Responsibilities:
o Architected the design and Implemented RTL using Verilog HDL.
Intern at Bhavini Nuclear Power Plant and underwent training below areas o MATLab Programming and Application
o Worked with Signal, Analysis of Discrete Time LTI o Learnt installation and programming of model Altivar 31 controller.
Designed, programmed and implemented Trolley
o Implemented Numerical Methods concepts in programming o Altivar31 Adjustable Speed Driver Controllers
VLSI Domain Skills
HDL : Verilog
HVL : System Verilog
Verification Methodologies : Coverage driven & Assertion based Verification TB Methodology : UVM
Protocol : SPI and AMBA
EDA Tool : Questasim and ISE
Domain : ASIC/FPGA front-end Design and Verification Knowledge : RTL Coding, FSM based design, Simulation, Code Coverage, Functional Coverage, Synthesis,
Static Timing Analysis
Technical Skills
High-level Language’
: C, C++
Low level Language : Microprocessor ( x86), MicroController, ARM7 TDMI, ARM 9 TDMI Assembly, x64 Basic
Digital Design Language : Verilog and System Verilog Verification
Methodologies
: Universal Verification Methodology(UVM)
Scripting Langauage : Perl
Tools and Hardware Knowledge and Used
Develop
Environment
: XiLinx ISE, Aldec Riviera –pro
Designing Tool : MicroWind, Tanner, LabView
Platform Used : Arduino ARM platform
Declaration
I, hereby declare that all the information given above is true to my knowledge
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