R Kumaran

Design engineer

ac2pvy@r.postjobfree.com

720*******

SUMMARY

M.tech with 2.3 Years of experience in FPGA Design Engineer. Worked on module architec- ture design, RTL coding and simulation. Worked on synthesis and implementation.

Experience in FPGA validation.

AREA OF INTEREST

ASIC RTL design and validation.

FPFA RTL design and validation.

EXPERIENCE SUMMARY

Currently working as “FPGA validation engineer” for Atlas systems Pvt ltd in client location

“L&T Technology services” since July 2017.

Worked for Unicorn Controls as Application Engineer from June 2013 to June 2015. WORK SUMMARY

Experience as RTL Design Engineer from last 2.3 years.

Experience in SoC based design, micro-architecture design, RTL Coding(Verilog), synthesis, simulation, place and route.

Basic knowledge on system verilog.

Worked on standard industrial protocols like I2C, SPI & UART.

Board Used: Spartan,virtex.

Experience in Client Communication and Status Reporting. Worked in high pressure conditions.

Good written and oral communication skills.

SKILLS

HDL Verilog

Bus Protocol AMBA AXI, AHB,APB

Serial Protocol SPI, I2c, UART

EDA Tool Tanner tools

Domain ASIC/FPGA Design Flow, Digital Design

Knowledge RTL Coding, FSM based design, Simulation. CERTIFICATIONS

Certification on “VLSI design and verification” from VinTrain academy, Chennai in the year 2013.

The duration of the course was from August 2012 to February 2013.

Concepts of CMOS technology.

Programming using verilog and implementation in the FPGA board.

Basics of system verilog.

PUBLICATIONS

Paper published in “International Conference on Intelligent computing and communication, 2017” on “ An FPGA implementation of Unified forward and inverse architecture of 4 to 32 point DCT”.

PROJECTS

1. Leanardo Project

Work done:

Responsible for the validation on Profpga board.

Generate bit file and resolving timing violation. 2. Communication Protocols Augmentation in VLSI Design Applications

The working of protocols like SPI, UART and I2C.

Implementation of communication protocol in FPGA board. 3. Falcon Control FPGA

Work done:

Developed the architecture for controlling the peripheral devices through software (CPU).

Developed the RTL model for the register control, address decoder, controller for periph- eral devices via standard protocol like I2C, SPI and LPC. 4. M.Tech project in VLSI front end design, “An FPGA implementation of unified forward and inverse architecture for 4 to 32 point DCT”.

o The DCT architecture was designed and implemented in the first phase of the project. o In the second phase the DCT architecture was modified in order to reduce the area of the architecture.

EDUCATION

M.Tech in “VLSI and Embedded systems Engineering” from “B.S.Abdur Rahman Uni- versity, Chennai” with cgpa 8.27 in 2017.

Bachelor of Engineering in “Electronics and Communication” with First Class from R.M.K. Engineering College, Chennai in the year of 2012 with cgpa 6.57.

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