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Cadence resumes in Mumbai, Maharashtra, India

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c,c++ in Linux platform,RTOS,8051,ARM

Mumbai, MH, 400078, India
... Tools Known: Model-Sim, XILINX-14, Cadence, Linux, Keil. Area of Interests: Embedded System, Linux, Concepts of RTOS. Operating Systems: Windows XP, Vista, 7, 8, Ubuntu 14.04 . "Chip Identification Generator By Butterfly- PUF With RO" May 2014 . ... - 2015 Jan 06

VSLI design &verification as per attached resume

Mumbai, MH, India
... Technical Skills Experience in Cadence EDA tool suite (Virtuoso). • Familiar with Synthesis Flow. • Stock with Physical design Flow and STA (Static Timing Analysis). • Low power VLSI design (circuit techniques, voltage scaling techniques, clock ... - 2014 Nov 30

Information Technology School

Mumbai, MH, India
... Centenary public school, New Delhi CBSE 8.2 GPA - Skills Expertise Area MicroController, Embeded system Programming C, Python, Matlab Language Tools and LT Spice, Matlab, Cadence, Advanced Design System (ADS) Technologies Operating System Windows, ... - 2014 Nov 06

High School Project

Mumbai, MH, India
... (Analog) Tools : CADENCE 3. Image Encryption and Decryption Using Symmetric Key Sequence of Elliptic Curve Over Prime Field Programming Language : MATLAB Tools : MATLAB R2012a Elliptic curve cryptography is one of the emerging and most popular ... - 2014 Oct 28

FPGA design, Verilog, ASIC design, Altera Quartus II

Mumbai, MH, India
... TECHNICAL SKILLS Hands On Experience Software Tools Programming Languages Cadence – NC Launch, RTL Complier C, C++ Cadence – SoC Encounter (Back-end) Verilog Mentor Graphic- Model-Sim PERL Altera Quartus – II TCL Cadence – Virtuoso W orked on – 45nm ... - 2014 Oct 27

Design Engineer

Mumbai, MH, India
... : Verilog and SystemVerilog Software Languages : C and assembly language EDA Tools Experience : o Full Custom tools: Cadence: o Virtuoso 6.1 o Calibre ( DRC, LVS, PEX, Compatibility check, ERC) o Physical Design Tools: Synopsys - IC Compiler o ... - 2014 Sep 23

Project Training

Mumbai, MH, India
... CMOS Aggregate : 63.5% Tools: PSPICE Keil uVision, Academic Profile Proteus Higher Secondary Certificate Examination - 12th (Science Cadence Field) CBSE Board Xillings Total Percentage = 69.6% Questasim Secondary Certificate Examination - 10th Magic ... - 2014 Sep 23

VLSI ENGINEER

Mumbai, MH, India
... C, C++, VHDL, Verilog HDL, Embedded C Cadence, Xilinx, MAT LAB, OrCAD, LT Spice, ModelSim, LPCXpresso, Codeblocks(GCC- compiler), AVR Studio, Code Composer Studio (CCS), Silos, Logisim Low Power VLSI, VLSI Subsystem Design, Digital System ... - 2014 Sep 21

Project Design

Mumbai, MH, 400078, India
... PCB was designed using Allegro (Cadence) software, Gerber edit using CAM350 software. The steps involved from designing till testing were Schematic capture, BOM Generation, Footprint Generation, Layout preparation of PCB, Gerber Generation, design ... - 2014 Jul 30

High School Engineering

Mumbai, MH, India
... Operating System : Windows EDAs : Tanner, T-spice, Cadence- Virtuoso, Xilinx (sim-ISE-9.2I syn-XST), Keil Handled SUBJECT’s and LAB’s * Electro Magnetic Theory & Transmission Lines (EMTL) * VLSI Design & lab * Electronics Devices & Circuits (EDC) & ... - 2014 Jul 01
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