c,c++ in Linux platform,RTOS,8051,ARM

Maulik B. Chauhan

E-Mail :- acg9oq@r.postjobfree.com

Mobile :- +91-895*******

* ** ****** * *********** position in the field of industry where I

can utilize my skills to the best of my ability and also at the same

time learn and use newly emerging technologies thereby ensuring

organizational and personal growth.

Education Specialization Board/University College/School Year Of CGPA /

Passing Percentage

M.Tech. VLSI Design SRM University, SRM University, 2014 7.895

Chennai KTR Campus,

Chennai

B.Tech. ECE GANPAT U.V.Patel College 2011 68.87%

UNIVERSITY,Gujara of Engineering,

t Mahesana

H.S.C. Physics, Gujarat Board P.V. Modi High 2007 63.20%

Chemistry, (G.S.H.S.E.B.) School

Maths, Hindi,

English,

Computer

S.S.C. Matriculation Gujarat Board S.V Virani School 2005 77.71%

(G.S.H.S.E.B.)

Programming Languages: Programming in C & C++ with Linux, Embedded

C, 8051, ARM, VHDL.

Tools Known: Model-Sim, XILINX-14, Cadence, Linux,

Keil.

Area of Interests: Embedded System, Linux, Concepts of

RTOS.

Operating Systems: Windows XP, Vista, 7, 8, Ubuntu

14.04

. "Chip Identification Generator By Butterfly- PUF With RO"

May 2014

. Physically unclonable functions (PUF) are commonly used in

applications such as hardware security and intellectual property

protection. Various PUF implementation techniques have been proposed

to translate chip-speci?c variations into a unique binary string. It

is difficult to maintain repeatability of chip ID generation,

especially over a wide range of operating conditions. To address this

problem, we propose utilizing con?gurable ring oscillators.

. Application was developed using Model-sim, Xilinx with Cadence tools.

. " NETWORK MANAGEMENT SYSTEM"

May 2011

. The Final semester project done at SIS (Sai-info System) company.

. Completed Training at Vector India Institute, Bangalore.

. Project executed of "RFID Based TOLL-GATE" system in Vector India.

. Published Paper: "Chip Identification Generator by Butterfly-PUF with

RO" Volume 05, Page no.794, Article 0341; IJVES-Y14-03241, March 2014,

ISSN: 2249-6556.

. Attended a 2-day workshop of animation under the IEEE in the

premises of GANPAT University on 7th and 8th of January 2010.

. Performing a Poster presentation on "GRID TECHONOLOGY" under

Electra in Convergence 2010.

. Performing a Project presentation on "Wireless Battery Charger"

under Electra in Convergence 2010. Visited Mahesana G.I.D.C in 3rd

semester (June 2008).

. Visited BSNL Exchange Mahesana in 6th semester (March, 2010).

. Attend one day Workshop on DIGITAL Signal Processing (DSP-10) under

GANPAT University on 11th December 2010.

. Certified in LATeX test conducted by IIT-BOMBAY at SRM University.

Date of Birth: 4th August, 1989

Father's Name: Mr. Bhupendrabhai Chauhan

Marital Status: Unmarried

Languages Known: English, Hindi and Gujarati

Current Location: "JAY MATAJI", NO. 12/35, WANKET, LAXMI-

KRUPA,3rd MAIN,11thCROSS,

J.P. NAGAR 1st PHASE,Bangalore-560078, Karnataka,

India.

Permanent Address: "DHANLAXMI", NIDHI Karmachari Soci., n/r

ALAP heritage, kalawad road,

Rajkot-360005, Gujarat, India

Hobbies: Web Surfing, Playing PC games, Reading

Magazines, Watching Movies.

I hereby declare that all the above-mentioned information is true to

the best of my knowledge. All necessary certificates and mark sheets I

will provide you at the time of personal interview.

Place:-

[Maulik B.

Chauhan]

[pic]

Career Objective

Educational Qualification

Projects Undertaken

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Technical Skills

Personal Details

Publications

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Training Undertaken

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