| Resume alert | Resumes 21 - 30 of 52 |
Design Training
Mumbai, MH, 400078, India
... Cadence tool suite :Virtuoso Schematic Editor, Virtuoso. Layout Editor,SOC Encounter, NC-Verilog. Synopsis Tool Suite :Design Compiler,Design Analyzer. Software skills :C,Cpp. Platforms :Linux, Windows. Architecture :µP 8085,86 Assembly Programming ... - 2016 Jan 19
... Cadence tool suite :Virtuoso Schematic Editor, Virtuoso. Layout Editor,SOC Encounter, NC-Verilog. Synopsis Tool Suite :Design Compiler,Design Analyzer. Software skills :C,Cpp. Platforms :Linux, Windows. Architecture :µP 8085,86 Assembly Programming ... - 2016 Jan 19
Engineering School
Mumbai, MH, India
... Attended the National Level Workshop on “Advanced Digital Logic Design using CADENCE EDA Tools”. Presented and won second prize among 113 papers submitted for the paper “Implementation of Nano technology based on VLSI” at a national level technical ... - 2015 Nov 21
... Attended the National Level Workshop on “Advanced Digital Logic Design using CADENCE EDA Tools”. Presented and won second prize among 113 papers submitted for the paper “Implementation of Nano technology based on VLSI” at a national level technical ... - 2015 Nov 21
Project Training
Mumbai, MH, India
... Tools : Cadence Virtuoso schematic editor & Digital encounter, Matlab Questasim, Modelsim, Xilinx. ACHIEVEMENTS AND TRAININGS: Participated in school annual Rally and Ravel at Shanthi Gruha SHQ conducted by The Bharat scouts and guides Karnataka. ... - 2015 Nov 04
... Tools : Cadence Virtuoso schematic editor & Digital encounter, Matlab Questasim, Modelsim, Xilinx. ACHIEVEMENTS AND TRAININGS: Participated in school annual Rally and Ravel at Shanthi Gruha SHQ conducted by The Bharat scouts and guides Karnataka. ... - 2015 Nov 04
verilog,logic design, Digital electronics, cadence, C and C++
Mumbai, MH, India
*th August **** Poornima A #*** *** ***** **************** K R Hospital Road Mysore 570001 Contact no:+91-988*******; Email id: acq9wq@r.postjobfree.com Respected Sir, I am submitting here with my resume for your perusal and favorable consideration... - 2015 Aug 17
*th August **** Poornima A #*** *** ***** **************** K R Hospital Road Mysore 570001 Contact no:+91-988*******; Email id: acq9wq@r.postjobfree.com Respected Sir, I am submitting here with my resume for your perusal and favorable consideration... - 2015 Aug 17
Project Design
Mumbai, MH, India
... 71.20 Academic project in M.tech: “High Speed Performance Wallace Tree Multiplier Using Booth 3 Algorithm” Academic project in BE: “Exhaust Gas Detection Using Zig Bee Technology” Workshop attended on: “ANALOG and DIGITAL VLSI DESIGN” using CADENCE ... - 2015 Jul 18
... 71.20 Academic project in M.tech: “High Speed Performance Wallace Tree Multiplier Using Booth 3 Algorithm” Academic project in BE: “Exhaust Gas Detection Using Zig Bee Technology” Workshop attended on: “ANALOG and DIGITAL VLSI DESIGN” using CADENCE ... - 2015 Jul 18
VLSI fresher with knowledge of RTL coding, cmos concepts etc.
Mumbai, MH, India
... VLSI Domain Skills HDL : Verilog EDA tools : ModelSim, Xilinx ISE 14.7, HSPICE 2008.03, Cadence Virtuoso & encounter (basic), Tanner EDA v13.0 Knowledge: RTL Coding, VLSI design flow, ASIC flow, CMOS concepts. Professional Qualifications Completed ... - 2015 Jul 01
... VLSI Domain Skills HDL : Verilog EDA tools : ModelSim, Xilinx ISE 14.7, HSPICE 2008.03, Cadence Virtuoso & encounter (basic), Tanner EDA v13.0 Knowledge: RTL Coding, VLSI design flow, ASIC flow, CMOS concepts. Professional Qualifications Completed ... - 2015 Jul 01
Design High School
Mumbai, MH, India
... COMPUTER SKILLS • Languages: Verilog HDL, System Verilog • Methodology: UVM • EDA Tools: Cadence, Modelsim, Synopsys • Operating Systems: WINDOWS, LINUX • Scripting Languages: PERL • Other Software : M S Office AWARDS & ACHIEVEMENTS • First prize, ... - 2015 Apr 23
... COMPUTER SKILLS • Languages: Verilog HDL, System Verilog • Methodology: UVM • EDA Tools: Cadence, Modelsim, Synopsys • Operating Systems: WINDOWS, LINUX • Scripting Languages: PERL • Other Software : M S Office AWARDS & ACHIEVEMENTS • First prize, ... - 2015 Apr 23
Project Engineer
Mumbai, MH, India
... 2) Participated in "low power VLSI design using CADENCE tools" on 27-2- 2013 and 7-3-2013 conducted by IETE student forum Chennai network in DR.M.G.R.Educational and Research Institute Universuty,Chennai-95. Project Handled: B.E (ECE) TITLE : ... - 2015 Mar 29
... 2) Participated in "low power VLSI design using CADENCE tools" on 27-2- 2013 and 7-3-2013 conducted by IETE student forum Chennai network in DR.M.G.R.Educational and Research Institute Universuty,Chennai-95. Project Handled: B.E (ECE) TITLE : ... - 2015 Mar 29
Engineer Design
Mumbai, MH, India
... Layout Tools Microwind, CADENCE (Virtuoso, Assura, Spectra). VLSI Tools Xillinx, Altera Quartus II. Others FPGA: Spartan-3E, Virtex-4, CycloneII & IV; Protocols: UART, DDR3, PCIe, USB, Ethernet. Certification and Publication . Published Paper: Avik ... - 2015 Mar 12
... Layout Tools Microwind, CADENCE (Virtuoso, Assura, Spectra). VLSI Tools Xillinx, Altera Quartus II. Others FPGA: Spartan-3E, Virtex-4, CycloneII & IV; Protocols: UART, DDR3, PCIe, USB, Ethernet. Certification and Publication . Published Paper: Avik ... - 2015 Mar 12
Design Engineering
Mumbai, MH, India
... Worked on Cadence Virtuoso tool (Version: IC 6.1.4) for Analog Circuit Simulation. Worked on tools like Microcap, Keil for Embedded C, MATLAB. ACADEMIC PROFILE Title of the Degree with Branch M.Tech Electronics Engineering SGGSIE&T, Nanded. ( An ... - 2015 Jan 18
... Worked on Cadence Virtuoso tool (Version: IC 6.1.4) for Analog Circuit Simulation. Worked on tools like Microcap, Keil for Embedded C, MATLAB. ACADEMIC PROFILE Title of the Degree with Branch M.Tech Electronics Engineering SGGSIE&T, Nanded. ( An ... - 2015 Jan 18