VSLI design &verification as per attached resume
Resume:
RESUME
CHOUDHARY ANUPAM G.N Email ID: ************@*****.***
S/o G.N.CHOUDHARY Mobile: +91-750*******
Chintamani apt, Plot no 421/1b
Flat no 501, Takka Panvel
Navi Mumbai-410206
Objective
To build a career in VLSI Design with a leading VLSI Design firm, where harmony between
professional and personnel goal is the key to shared success and continuous opportunities are
available towards the development of my technical, professional and interpersonal expertise.
Technical Skills
Experience in Cadence EDA tool suite (Virtuoso).
•
Familiar with Synthesis Flow.
•
Stock with Physical design Flow and STA (Static Timing Analysis).
•
Low power VLSI design (circuit techniques, voltage scaling techniques, clock gating, glitch
•
power analysis).
Languages C, Verilog.
Software Proficiency Familiar Platforms Multisim, Modelsim, LTspice, Libero, Quartus.
Operating Systems Red HAT, Windows, Macintosh
Projects and Seminar
1) To Design and test Seismic Switch based on MEMS (Internship)
Description:
A system, which senses the Vibration via MEMS, placed at the field. It is controlled and
monitored from the remote location. When the Vibration exceeds the set threshold value, system
will generate the alarm. System is enhanced with self-test features, Reliability, ruggedness,
availability and Observability.
2) “Low Frequency Low gm CMOS OTA-C Filter for Biomedical Applications”(MSc Tech)
Team Size: 3
Tool: Cadence 6.1.5v
Description:
Much of biomedical signals need high quality low pass filters for better signal processing. This
project is intended to present a few non-conventional techniques developed so far such as Floating
Gate (FG), Bulk Driven (BD), Source Degeneration (SD), and Current Division (CD) to arrive at
low gm OTA and some linearization techniques which serves the purpose of better low frequency
filtering. A detailed comparison has been made among these techniques in terms of various
performance parameters such as gm, power consumption, input referred noise, supply voltage and
many more.
3) “Redefining
CMOS
Logic
Style
for
Sub-
threshold
Operation”(MSc Tech)
Team Size: 3
Tool: Cadence 6.1.5v
Description:
Sub-
threshold
design
of
CMOS
logic
circuits
is
important
for
ultra-
low-
power
operation.
With
continuous
scaling
of
MOS
devices
to
nanometer
sizes
however,
conventional
CMOS
logic
style
may
not
function
properly
at
65nm
and
below
due
to
a
variety
of
leakage
currents
flowing.
In
this
work,
a
new
CMOS
logic
style
that
results
in
reduced
leakage
currents
both
in
active
and
idle
modes
of
operation
leading
to
a
better
static
and
dynamic
performance
is
proposed.
Simulations
have
been
carried
out
in
Cadence
to
verify
the
functionality
of
the
gates
using
standard
180nm
technology.
Results
indicate
that
static
power
reduction
of
up
to
25%
has
been
achieved.
4) Confer a Seminar on UPF (Unified Power Format) (MSc tech)
Description:
Static or leakage-based power consumption requires new techniques and standards that fall
outside the scope of traditional HDL-based flows. The IEEE Standard 1801-2009, based on
Accellera’s Unified Power Format (UPF), allows designers to describe low power design intent
and improve the way complex integrated circuits can be designed, verified and implemented.
Discussed features of UPF (1.0), Isolation strategies, Retention register, level shifters and
limitations of UPF 1.0.
5) Presented a Seminar on UVM (Universal Verification Methodology) (MSc tech)
Description:
The Universal Verification Methodology (UVM) is a standardized methodology for verifying
integrated circuit designs. The UVM class library brings much automation to the System Verilog
language such as sequences and data automation features (packing, copy, compare) etc. Discussed
UVM environment and verification components.
6) BE project Microcontroller based robot June 2008 – Mar 2009
application in military.
7) BE Mini project PC based sound measurement. Jan 2008 – Mar 2008
Paper
1) Journal “Analog Integrated Circuit and Signal Processing” by Springer: - Paper titled “A Survey on
Low gm OTA Designs for Low Frequency Applications” is before the editorial board of Springer.
Work Experience
1) Oasis Technologies: - Advanced Embedded System Design (6 months) three months training and
three months internship.
2) Mashal Shipping Agency :- (5 Month) Training at Bangkok followed by 12 Month experience.
Training and Workshop
1) Digitech Solutions (Bangalore): - Workshop (State level) on VLSI technologies (5 days).
2) Nuclear Power Corporation India Limited (NPCIL): - Study On Nuclear Power Plant Simulator (15
days).
3) AAI (Airport Authority of India) Mumbai: - Study on ILS (Instrument Landing System) (11 days).
4) Technical Symposium (Hyderabad): - Participated in Project exhibition (National level) and secured
third prize.
5) NIIT Mumbai: - workshop on Programming C (8 days).
6) IARE Aurangabad: - Workshop on C–interfacing and electro pneumatic (3 days)
Extra-curricular
1) Attended and passed the general knowledge and intelligence test conducted by CENTRAL
INSTITUTE OF GENERAL KNOWLEDGE at junior and senior level.
2) “Adventure and Nature Awareness Camp” by DAE sports and cultural council at Anushaktinagar
MUMBAI (8 days).
Educational qualification
Year of
Course Name of Institute Board/University Marks%
Passing
1st/2nd sem
MSc Tech (VLSI Manipal In
School of Information Sciences
Design) University progress 8.04/8.36
BE (E & TC) Pravara Rural Eng. College Pune university 2009 61.2
HSC Atomic Energy Central School CBSE Board 2003 56.3
SSC Atomic Energy Junior College State board 2001 60
Areas of interest
Digital design, Analog design.
Hobbies
Swimming, Reading, Morning walk.
Personal profile
Father’s Name : G.N.CHOUDHARY
Date of Birth : 25 Aug 1986
Sex : Male
Languages Known : English, Maithili and Hindi.
Nationality : Indian
Permanent Address : S/o G.N.CHOUDHARY
Chintamani apt, plot no 421/1b
Flat no 501, Takka Panvel
Navi Mumbai-410206.
Declaration
I hereby declare that the information furnished above is true to the best of my knowledge.
Place: Mumbai
Date: 18 Nov 2014 ` Choudhary Anupam G N
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