| Resume alert | Resumes 41 - 50 of 52 |
Power Engineer
Mumbai, MH, India
... WORK OUTLINE: VLSI Fundamentals, CMOS Basics, latch up issues, Floor Planning, Placement and Routing, Analog Layout, matching techniques,Cadence virtuoso tool editor, deep sub micron technologies issues,tapeout. SUMMARY: Hands on 1 YEAR 2 months ... - 2014 Jun 28
... WORK OUTLINE: VLSI Fundamentals, CMOS Basics, latch up issues, Floor Planning, Placement and Routing, Analog Layout, matching techniques,Cadence virtuoso tool editor, deep sub micron technologies issues,tapeout. SUMMARY: Hands on 1 YEAR 2 months ... - 2014 Jun 28
Project Years Experience
Mumbai, MH, India
... Expertise in Cadence digital design. Roles Played: Activities & Achievements: Placement committee Head. Symposium Coordinator. Exam Cell Member. RRC committee member. Organizer of the curricular activities. Project Coordinator. Subjects handled: ... - 2014 Jun 01
... Expertise in Cadence digital design. Roles Played: Activities & Achievements: Placement committee Head. Symposium Coordinator. Exam Cell Member. RRC committee member. Organizer of the curricular activities. Project Coordinator. Subjects handled: ... - 2014 Jun 01
Engineer Design
Mumbai, MH, India
... TECHNICAL SKILLS o Programming Languages: Unix Shell, SKILL, PERL o Layout tools: Cadence virtuoso layout editor. o LVS/DRC tools: Assura LVS/DRC/RCX, K2 Verification Simulation Tools: NGSPICE, CADENCE(CDB and Open access – OA) o o Application ... - 2014 May 30
... TECHNICAL SKILLS o Programming Languages: Unix Shell, SKILL, PERL o Layout tools: Cadence virtuoso layout editor. o LVS/DRC tools: Assura LVS/DRC/RCX, K2 Verification Simulation Tools: NGSPICE, CADENCE(CDB and Open access – OA) o o Application ... - 2014 May 30
Skill Set: Verilog Hdl, Cadence Tools.
Mumbai, MH, India
... COLLEGE M.P.C 84.90% E 2008 73.00% SSC MADHU MALANCHA HIGH 2006 SCHOOL Technical Skills: Languages: C, Core java Knowledge about 8051 micro controllers, EMBEDDED C Packages: VERILOG HDL, CADENCE TOOLS Computer hardware & networking ACHIEVEMENTS: . ... - 2014 May 18
... COLLEGE M.P.C 84.90% E 2008 73.00% SSC MADHU MALANCHA HIGH 2006 SCHOOL Technical Skills: Languages: C, Core java Knowledge about 8051 micro controllers, EMBEDDED C Packages: VERILOG HDL, CADENCE TOOLS Computer hardware & networking ACHIEVEMENTS: . ... - 2014 May 18
Electrical Engineer Power Plant
Mumbai, MH, India
... From 11th March 2013 to Still doing on the site of CADENCE DESIGN SYSTEM Looking Following Responsibility: • Making Daily & Monthly consumption Report including (Inventory, Power Consumption & Diesel Consumption). • Installation, Erection & ... - 2014 May 07
... From 11th March 2013 to Still doing on the site of CADENCE DESIGN SYSTEM Looking Following Responsibility: • Making Daily & Monthly consumption Report including (Inventory, Power Consumption & Diesel Consumption). • Installation, Erection & ... - 2014 May 07
Engineer Project
Mumbai, MH, 400078, India
... EDA Tools: Cadence (Virtuoso), • Virtuoso XL, Stabie soft. WORK HISTORY Trainee Analog & Mixed signal Layout Engineer October 2012 to February 2014 ARF Design Pvt ltd Bangalore Topics covered were: • Basics of semiconductors devices. • Fabrication ... - 2014 Apr 23
... EDA Tools: Cadence (Virtuoso), • Virtuoso XL, Stabie soft. WORK HISTORY Trainee Analog & Mixed signal Layout Engineer October 2012 to February 2014 ARF Design Pvt ltd Bangalore Topics covered were: • Basics of semiconductors devices. • Fabrication ... - 2014 Apr 23
Design Engineer
Mumbai, MH, India
... Skill Set EDA Tools : Cadence Virtuoso Spectre Simulator IC6.1 Version Layout design Hardware Description Languages : Verilog, system Verilog. : C & C++, Micro wind software lab, Basic knowledge Software Skills Java Platforms : LINIX, UNIX, Windows. ... - 2014 Feb 16
... Skill Set EDA Tools : Cadence Virtuoso Spectre Simulator IC6.1 Version Layout design Hardware Description Languages : Verilog, system Verilog. : C & C++, Micro wind software lab, Basic knowledge Software Skills Java Platforms : LINIX, UNIX, Windows. ... - 2014 Feb 16
Mtech E&TC student . VHDL,Verilog,system verilog programming languages
Mumbai, MH, India
... Tools: FPGA Tools : Xilinx 14.1, EDK, Cadence NC-sim, mentor graphics. Spice Tools : Ngspice, pspice Other Tools : MATLAB, Keil, Microcap, Microwind, Express PCB Devices Handled : Microcontrollers: 8051, ARM, PIC FPGA Kit-spartan & vertex, Embedded ... - 2013 Oct 25
... Tools: FPGA Tools : Xilinx 14.1, EDK, Cadence NC-sim, mentor graphics. Spice Tools : Ngspice, pspice Other Tools : MATLAB, Keil, Microcap, Microwind, Express PCB Devices Handled : Microcontrollers: 8051, ARM, PIC FPGA Kit-spartan & vertex, Embedded ... - 2013 Oct 25
Engineer Design
Mumbai, MH, 400063, India
... IC Layout Design : Micro Wind, Cadence(Virtuoso), Laker basic Tool knowledge OS : Windows, Linux overview Scripting Language : Basic knowledge of Skill EXTRA CURRICULAR . Secured 3rd position in the Late Shree Chandrakant Shah Memorial Skating ... - 2013 Jun 22
... IC Layout Design : Micro Wind, Cadence(Virtuoso), Laker basic Tool knowledge OS : Windows, Linux overview Scripting Language : Basic knowledge of Skill EXTRA CURRICULAR . Secured 3rd position in the Late Shree Chandrakant Shah Memorial Skating ... - 2013 Jun 22
Project Pvt Ltd
Mumbai, MH, India
... C ode Coverage T esting with ICC (Cadence). P rogram Management i nvolves p) MPS q) Process Defining and Deployment r) Team Management A ctivity: S ignal Integrity and IBIS model generation & Validation at Chip Level • D evelopment and Validation of ... - 2013 Feb 27
... C ode Coverage T esting with ICC (Cadence). P rogram Management i nvolves p) MPS q) Process Defining and Deployment r) Team Management A ctivity: S ignal Integrity and IBIS model generation & Validation at Chip Level • D evelopment and Validation of ... - 2013 Feb 27