Project Design
Resume:
CURRICULUM VITAE
Kavita Uttam Koli
4th main road,19th Cross street,
Ramesh Nagar
Bangalore-37
Contact No: +91-758******* / +91-991*******
Email id: ******.****@*****.***
CAREER OBJECTIVE:-
1
My career objective is to combine my acquired knowledge with my desire to learn and make a difference to
the organization.
CAREER S UMMARY :-
2
Project Trainee at Aeronautical Development Agency, Bangalore July 2013 – Dec2013
Project Undertaken:
Title: Automation system for 1553B Bus Analysis
Aeronautical Development Agency (ADA) is a Research laboratory of DRDO, responsible for design and
development of indigenous Light Combat Aircraft (LCA), Tejas.
Responsibility: Design of automation system and testing it for various configurations of aircraft.
The project aims to develop an automation system for 1553 Bus. 1553B Bus is used for avionics system units
to be connected in a network. Automation helps to manage the complexity of the huge data flows among the
network. A system consist of four subsystems namely bus load analysis system, Bus load optimization
system, Scheduler table verification system and air data computation system.
Bus load analysis system analyses the data bus loading by simulating the real time communication
operation between units connected to 1553 network. Bus load optimization system optimizes the load for
uniform distribution among the minor cycles. A scheduler table verification system analyses whether the data
transferred is according to the scheduled one. Air data parameter computation system is alternative system to
the Air data parameter computation system developed in ADA.
Tool Used: MATLAB
P G Diploma in VLSI design at C-DAC ACTS, Pune Aug 2011 – Jan 2012
I have completed P G Diploma in VLSI Design at C-DAC ACTS, Pune.
Project Undertaken:
Title: Design of DMA Controller and its implementation on FPGA
The objective of the project was to design a controller combining features of existing 8257 and 8237
controllers. DMA Controller is designed for transfer of data directly between peripheral device and
memory without intervention of processor. Direct data transfer improves system performance. The
steps carried out for the completion of project are given below
1) DMA controller was designed using VHDL and its functionality was verified using Verilog.
2) The simulation of the controller was done using Questasim(6.6d). The design of DMA
controller was verified using the environment as shown below.
a) Verification of PRIORITY RESOLVER was done with multiple requests.
b) Verification of data transmission done by checking contents of control registers and
memory.
3) Xilinx ISE Design Suit 12.2 was used for synthesis of the design . The performance
parameters of controller obtained after synthesis is fairly good.
Tools Used: Xilinx, Questasim
Project Undertaken:
1) Implementation of combinational circuits includes adder/subtractor, Multiplexer, Demultiplexer,
Encoder, Decoder, Comparator and ALU.
2) Implementation of sequential circuits includes Laches, Flip flops, Counters, Shift registers.
3) Parity Generator Circuit, Barrel Shifter
4) Implementation of Memories
-Single port RAM
-Dual port RAM
5) Implementation of Multipliers
-Add and Shift Algorithm
-Booths multiplier
6) Scheduling algorithms including LRU, Fixed Priority, and Round robin.
7) Implementation of First In First Out (FIFO) Buffer.
8) State machine implementation including Edge Detector, Sequence detector.
Sahyadri Polytechnic, Pune May2010-July 2011
I worked as a Lecturer in Electronics and Telecommunication Department. I taught digital electronics
and basic electronics subjects. I also took laboratory for the subjects which I taught.
Interfab ElectronicsPvt. Ltd. Mumbai July 2009- Feb 2010
I worked as PCB Design Engineer. My job responsibility was to design a PCB for various clients in a
stipulated time period. I was involved from designing phase to testing phase of PCB. PCB was
designed using Allegro (Cadence) software, Gerber edit using CAM350 software. The steps involved
from designing till testing were Schematic capture, BOM Generation, Footprint Generation, Layout
preparation of PCB, Gerber Generation, design editing, stencil checking, PCB checking. I also
prepared material for production like P & P (Pick & Place) data, manufacturing drawing.
EDUCATION CREDENTIALS :-
3
Board/Universit
Sr No. Exam College/Institute Year of Study % / CGPA
y
M.Tech
1 D.O.T. Kolhapur Shivaji University 2012-2014 7.3
(Electronics)
P.G.Diploma
2 C-DAC ACTS Pune - 2011 58
(VLSI Design)
B.E.
3 P.V.P.I.T, Budhgaon Shivaji University 200*-****-**
(Electronics)
H.S.C(Science J.N.V. Sangali
4 CBSE board 2003-2004 67.8
)
5 S.S.C J.N.V. Ratnagiri CBSE board 2001-2002 79.2
TECHNICAL PROFICIENCY:-
4
Programming Languages: C, VHDL, Verilog, Assembly language- 8085,8051.
Software:Questasim(6.6d), Xilinx ISE Design Suit 12.2, MATLAB, Code composer Studio v5, keil 2
ACADEMIC PROJECT
5
COMPLETED:-
Title: Design and implementation of reversible logic gates.
Reversible logic gates are designed for better performance.
Tool Used: Xilinx 14.2
HONOUR / ACHIEVEMENT :-
6
• GATE Qualified in 2011 with 88 percentile.
• 82 percentile for All India Entrance Test for C-DAC ACTS
CO-CURRICULAR ACTIVITIES :-
7
• Seminar on FPGA Design Issues.
• Seminar on B-Fetch Branch prediction Directed Prefetching for In-Order Processors.
• Participated in Industrial problem solving competition in Jinyasa 2013.
• Worked as Examination Incharge for Semester Exam in Sahyadri Polytechnic.
• Was involved in the work of paper checking for diploma semester examination at Pune University.
• Presented paper on 3G Technology in Nirmiti-National Level Paper Presentation.
• Completed basic course of “Landmark Education”
• Latex Software certified.
DETAILS:-
PERSONAL
8
9
10 Marital Status: Single
Hobbies: Cooking, Reading Books, Playing Badminton.
Languages Known: English, Hindi, and Marathi.
Strength: Honesty, Hardworking and quick learner.
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