NAZILA AREF SHENASI

Redondo Beach, CA ***** 310-***-**** adep51@r.postjobfree.com U.S. citizen

Objective: Seeking opportunities within the field of Electrical Engineering

WORK EXPERIENCE

Electrical Engineer, AEi Systems, Los Angeles, CA 07/2012-current

Providing product performance, quality, and reliability test to various customers in defense and aerospace industry.

Performing Worst Case Circuit Analysis (WCCA) and SPICE modeling

Analyzing power supplies and analog circuits, Developing test measurement workshops

Performing circuit test measurements using a variety of electronic laboratory instruments

Analyzing circuits using mathematical calculations with taking various part tolerances into account

Writing and reviewing technical reports with detailed analysis results for customers

Maintaining constant communication with customers to answer technical questions

SKILLS

CAD Tools: Cadence OrCAD, LabVIEW, ETAP, PSpice, Spectre, LTSpice, MATLAB

SPICE Modeling: Modeling Parts such as Tantulum/Ceramic Capacitors, Diodes

Hardware/Software Development: C/C++, VHDL, Verilog

Laboratory Equipment: Network Analyzer, Spectrum Analyzer, Phase Noise Analyzer, etc

Excellent presentation, documentation, and communication skills

EDUCATION

M.S. in Electrical Engineering, University of California, Irvine, CA December, 2013

Emphasis: Circuits, IC Design, Power Electronics GPA: 3.28

B.S. in Electrical Engineering, California State University, Los Angeles, CA June, 2011

Emphasis: Power, Electronics GPA: 3.86

Dean’s list: Fall 2009-Spring 2011

MAJOR COURSES

Electric Power Distribution, Power Transmission Lines, Electric Power System Analysis, Electrical Circuits I and II, Electromagnetics, Power Transmission Lines, Power System Analysis, Electromagnetic Energy Conversion. Digital Communication I, ADV Semiconductor DEV, Analog IC Design, RFIC design.

ACADEMIC PROJECTS

CSULA Projects

Southern California Edison - Energized Line Detector

Developed a warning system that detects electric fields around high-voltage overhead distribution power lines for multiple voltage levels

Designed a detector to provide a warning to operators when the aerial arm or bucket is moving in the direction towards the energized power line

UCI Projects

Clock Data Recovery (CDR)

Designed a clock CDR circuit for a SONET OC-48 application using a 0.18 µm standard CMOS process, which used a Phase lock loop (PLL) to align the data and clock signals at 2.5Gbps.

Operational Amplifier Design using a 0.13 μm CMOS process

Designed and simulated an Operational Amplifier with 60 dB gain and 3GHz bandwidth in Cadence Spectre Circuit Simulator

Phase-Locked Frequency Synthesizer Design using a 65 nm CMOS process

Designed and simulated a 100GHz CMOS frequency synthesizer with robust performance in the presence of supply or substrate noise

HONORS & MEMBERSHIPS

Memberships: IEEE, CSULA Student Chapter, Society of Women Engineers

Languages: English, Farsi, Turkish (Full professional proficiency)

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