Rajesh Sarkar

Los Angeles, CA Phone: 818-***-**** Email: adekce@r.postjobfree.com https://www.linkedin.com/in/rajesh-sarkar-rds311994/ Summary:

Experienced Design Verification engineer and a recent Electrical and Computer Engineering graduate student, seeking a full-time opportunity in ASIC/Digital/SoC Design Engineer, Design Verification Engineer, Firmware, Validation, Testing Starting Immediately.

Education:

Master of Science in Electrical and Computer Engineering, Dec 2019 California State University, Northridge (GPA 3.3/4) Courses: FPGA, System on Chip (SOC), Computer Architecture, Advanced Switching Theory, Digital System Auto VHDL, Diagnosis and Reliable Design of Digital Systems, Digital Communication, Image Processing. Bachelor of Engineering in Electronics, May 2016 University of Mumbai, India (GPA 7.01/10) Technical Skills:

Programming Languages : UVM, Verilog, System Verilog, C, C++, Python, Perl, SVA. EDA Tools : UVM Framework, ModelSim, Xilinx Vivado Design Suite, Cadence Virtuoso, Synopsys VCS Hardware : ZedBoard Zynq-7000 ARM/FPGA SoC Development Board, Xilinx FPGA Virtex 6, Arduino Uno. Work Experience:

Belkin International. CA, USA Design Verification Engineer (Volunteer) (JUNE 2019- DEC 2019)

• Performed regression, functional verification and developing test plans and test specifications for the controller side of a high-speed-communication interface of USB-A, USB-C, Ethernet, HDMI ((v1.4, v2.X), Thunderbolt using UVM.

• Written full chip Coverage model and Testbench architecture and have done verification of SOC till tapeout stage.

• Board level debugging and troubleshooting for digital logic and analog circuits on PCB using Oscilloscope, digital analyser.

• Participate in SoC Lab testing of the product, specifically for PCIe standard testing and debugging in Lab. HERE Technologies. INDIA RTL Design Engineer I (GIS) (DEC 2016- JULY 2017)

• Designed highspeed data path and control units and assisted in shaping the micro-architecture of chip.

• Block or Chip Level Floor planning, Bus / Pin Planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification and Sign Off.

• Developed RTL module in System Verilog which involved creating DRAM Memory controller and high-speed communication via SerDes to transfer data from FPGA to another, FIFO and DDR memory interface, Synthesis and place and route. Academic Projects:

Design and Verification (Languages: UVM, SystemVerilog, Verilog, SVA, C++) Design Verification of UART.

• Developed a UVM based testbench using System Verilog to verify the RTL of UART IP Core.

• Evaluated different modes Full-Duplex, Half-Duplex and Loopback mode successfully with functional coverage of 100%. Design of 5 Stage Linear Pipelined Processor

• Designed a 5-stage pipelined processor using Verilog supporting MIPS instruction set architecture. With an Instruction memory (256x16 bit), Data memory (8x16 bit) and Register file (8x16 bit) and 16-bit ALU.

• Control hazards, Structural hazards and Data dependencies solved using Hazard Detection Unit and Forwarding Unit FIFO Design for Clock Domain Crossing and verification using SVA

• Designed 0, 1, 2 and 8 register FIFO interfaces to exchange data between producer and consumer in different clock domains. Implemented with and without prefetched and overlapped production and overlap. Design and Verification of an AHB-Lite Protocol

• Led a team of 3 to design a synthesizable SV ABH-LITE dual-port RAM module with basic requirements of AHB peripheral.

• Developed verification environment and random based simulation derived the verification components. Verification of data and control path of Pipelined LC- 3 Microcontroller

• Designing a complete verification environment for LC3 Pipelined microcontroller with a comprehensive instruction set.

• Implementing randomized testbench and directed testbench to ensure absolute functional coverage. Verification of NOR Flash Memory Controller using WISHBONE Interface

• Developed Object-Oriented and basic UVM oriented test environments. Built stimulus generator, scoreboard, monitor, responder and coverage collectors. Verification of the system was done using constrained randomization. Coverage analysis was done for the internals along with the ports

Cache Hierarchy Simulator using python (Language : Python)

• Implemented cache with parameterized geometry (cache size, block size, associativity), replacement and inclusion property

• Designed to predict cache miss rates for different cache configurations when running different workloads Publications and Research work:

Intrabody Communication using Android Platform

• In ITSI Transaction on Electrical and Electronics Engineering (ITSI-TEEE) in volume 4 issue 1 in the year 2016. http://www.irdindia.in/journal_itsi/pdf/vol4_iss1/4.pdf

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