| Resume alert | Resumes 101 - 110 of 422 |
Project Fresh Graduate
Bangalore, Karnataka, India
... HTML Tools Worked On: Keli Octave Cadence Matlab Xilinx LabVIEW AREA OF INTREST Microprocessors,Microcontrollers(Embedded) Analog Electronic Logic design VLSI(Semiconductors) ACHIEVEMENTS Won a District Third Price In “Putani Vigynana” In 2010. ... - 2018 Sep 03
... HTML Tools Worked On: Keli Octave Cadence Matlab Xilinx LabVIEW AREA OF INTREST Microprocessors,Microcontrollers(Embedded) Analog Electronic Logic design VLSI(Semiconductors) ACHIEVEMENTS Won a District Third Price In “Putani Vigynana” In 2010. ... - 2018 Sep 03
Project Office
Marathahalli, Karnataka, India
... 2015 77% SSLC Sacred Heart Girl’s High School 2012 84.48% TECHNICAL SKILLS Programmimg Languages:C,C++,Embedded(8086,8051) Tools:Xilinx,Cadence,CCS Studio(MATLAB),keil microvision Office Package:MS Word,MS Power Point,MS Excel PROJECT DETAILS 1. ... - 2018 Aug 19
... 2015 77% SSLC Sacred Heart Girl’s High School 2012 84.48% TECHNICAL SKILLS Programmimg Languages:C,C++,Embedded(8086,8051) Tools:Xilinx,Cadence,CCS Studio(MATLAB),keil microvision Office Package:MS Word,MS Power Point,MS Excel PROJECT DETAILS 1. ... - 2018 Aug 19
Engineer Design
Bangalore, Karnataka, India
... -Software Used: Cadence Virtuoso in 130nm process technology. -Component Used: lvtnfet (MOSFET), capacitors. Good knowledge in NMOS, PMOS and CMOS VLSI circuits and also having experience in analog layout design using Cadence Virtuoso tool. Having ... - 2018 Aug 15
... -Software Used: Cadence Virtuoso in 130nm process technology. -Component Used: lvtnfet (MOSFET), capacitors. Good knowledge in NMOS, PMOS and CMOS VLSI circuits and also having experience in analog layout design using Cadence Virtuoso tool. Having ... - 2018 Aug 15
Industrial Training Project
Bangalore, Karnataka, India
... Tools: Experience in physical design of 130nm and 90nm technologies using Cadence tool Cadence SOC Encounter –Floor Planning, Place & Route, and clock tree synthesis Encounter Timing System –Static Timing Analysis and Cross-talk Analysis RTL ... - 2018 Jul 20
... Tools: Experience in physical design of 130nm and 90nm technologies using Cadence tool Cadence SOC Encounter –Floor Planning, Place & Route, and clock tree synthesis Encounter Timing System –Static Timing Analysis and Cross-talk Analysis RTL ... - 2018 Jul 20
VLSI Design, CMOS Technology, Cadence Virtuoso, Verilog
Bangalore, Karnataka, India
... Skills Digital IC/ASIC Design: Cadence Virtuoso, Xilinx ISE, Languages: Verilog DSCH, Cadence NClaunch Shell script: UEFI Analog Design: Cadence Virtuoso 64, TINA TI Platforms: Windows, Linux Layout tool: Encounter, Microwind CAD Design: Comsol ... - 2018 Jul 12
... Skills Digital IC/ASIC Design: Cadence Virtuoso, Xilinx ISE, Languages: Verilog DSCH, Cadence NClaunch Shell script: UEFI Analog Design: Cadence Virtuoso 64, TINA TI Platforms: Windows, Linux Layout tool: Encounter, Microwind CAD Design: Comsol ... - 2018 Jul 12
Information Security Engineering
Bangalore, Karnataka, India
... languages: C(Basics),C++(Basics), java, python, HDL programming, Matlab, 8051 microcontroller programming Software used : Cadence virtuso, pspice, xillinx, kiel-uVison, matlab, Microsoft Excel Awards/ Achievements Won the Second Place in Carrom at ... - 2018 Jun 20
... languages: C(Basics),C++(Basics), java, python, HDL programming, Matlab, 8051 microcontroller programming Software used : Cadence virtuso, pspice, xillinx, kiel-uVison, matlab, Microsoft Excel Awards/ Achievements Won the Second Place in Carrom at ... - 2018 Jun 20
Project Assembly Line
Bengaluru, KA, India
... Basic Embedded systems using keil, AVR, Cypress and Arduino (μC 8051, Atmega 8, Cypress - 5) Basic VLSI design using Cadence. MINI PROJECT DETAILS: TITLE: FAULT TOLERANT FULL ADDER/SUBTRACTOR USING REVERSIBLE LOGIC DESCRIPTION : Reversible logic is ... - 2018 May 31
... Basic Embedded systems using keil, AVR, Cypress and Arduino (μC 8051, Atmega 8, Cypress - 5) Basic VLSI design using Cadence. MINI PROJECT DETAILS: TITLE: FAULT TOLERANT FULL ADDER/SUBTRACTOR USING REVERSIBLE LOGIC DESCRIPTION : Reversible logic is ... - 2018 May 31
Project Security
Bengaluru, KA, India
... Simulation Tools : LTSpice, µVision Keil, ModelSim, Xilinx, Cadence, Matlab. Project (Diplomo): ”RFID BASED ATTENDANCE SYSTEM”. In this project For each person in instituition, industries, offices etc RFID card is given, When the person entered ... - 2018 May 16
... Simulation Tools : LTSpice, µVision Keil, ModelSim, Xilinx, Cadence, Matlab. Project (Diplomo): ”RFID BASED ATTENDANCE SYSTEM”. In this project For each person in instituition, industries, offices etc RFID card is given, When the person entered ... - 2018 May 16
Physical design trainee
Bengaluru, KA, India
... Other Tools : Xilinx ISE, Cadence Virtuoso, LABVIEW OS Platforms : Windows XP/7/8.1, Linux. PROJECT EXPERIENCE: Project 1 Technology / Layers : 28nm / 9 Metal Layers. Gate count/Area : 731376/1195801.62 um2 Macros : 20 STD Cells : 200075 No. of ... - 2018 Feb 25
... Other Tools : Xilinx ISE, Cadence Virtuoso, LABVIEW OS Platforms : Windows XP/7/8.1, Linux. PROJECT EXPERIENCE: Project 1 Technology / Layers : 28nm / 9 Metal Layers. Gate count/Area : 731376/1195801.62 um2 Macros : 20 STD Cells : 200075 No. of ... - 2018 Feb 25
Engineer Design
Bengaluru, KA, India
... Air Data Control computer Hardware Design Intel I960 processors interfaced with SRAM Schematics Design Orcad Captrure using Cadence software Hardware Testing Analogue Board : Servo interface and Discrete Interface module of LADC Projects Handled in ... - 2018 Feb 12
... Air Data Control computer Hardware Design Intel I960 processors interfaced with SRAM Schematics Design Orcad Captrure using Cadence software Hardware Testing Analogue Board : Servo interface and Discrete Interface module of LADC Projects Handled in ... - 2018 Feb 12