KISHORA NAIK S

Phone: +91-959*******

Email:ac4lru@r.postjobfree.com

CAREER OBJECTIVE:

To put my abilities and learning skills to best use and make my effective contribution to an organization for a bright and rewarding career.

PROFESSIONAL TRAINING:

Undergone Physical Design training from ChipEdge Technologies Pvt. Ltd, Bangalore, using Synopsys IC Compiler during November 2017 to February 2018. COURSE OUTLINE:

VLSI Fundamentals, CMOS Basics, Floor Planning, Power Planning, Placement, Clock Tree Synthesis, Routing, Timing analysis and Optimization, Physical Verification and ECO flow. Tools Used in the Training:

IC-Compiler, Star-RC, IC Validator, Prime Time.

EDUCATIONAL QUALIFICATIONS:

Master of Technology [VLSI Design & Embedded Systems] Dayananda Sagar College of Engineering, Bangalore, Autonomous. Graduated in 2017 with CGPA of 8.45.

Bachelor of Engineering [Electronics & Communication] Adichunchanagiri Institute of Technology, Chickmagaluru, VTU University. Graduated in 2015 with aggregate of 61.08%.

P.U.C, Karnataka PU Board

DVS [INDP] PU College, Shimoga, Karnataka

Graduated in 2011 with 61%.

SSLC, KSEEB

S.U.P.H.S, Chinnikatte, Karnataka

Graduated in 2008 with 74.8%.

TECHNICAL SKILLS:

Programming Language

: C, VHDL, Verilog.

EDA Tools : IC Compiler, Synopsys (Proficiency level: Beginner). Other Tools : Xilinx ISE, Cadence Virtuoso, LABVIEW OS Platforms : Windows XP/7/8.1, Linux.

PROJECT EXPERIENCE:

Project 1

Technology / Layers : 28nm / 9 Metal Layers.

Gate count/Area : 731376/1195801.62 um2

Macros : 20

STD Cells : 200075

No. of Clocks : 3

Frequency : 172.4 MHz

Tools Used : IC-Compiler, Star-RC, IC Validator, Prime Time Role : To perform Sanity checks, Floor Plan, Power Plan, Placement, CTS, Routing, Timing Analysis and Optimization, DRC, LVS. Project 2

Technology / Layers : 28nm / 9 Metal Layers.

Gate count : 50K

Macros : 6

STD Cells : 10K

No. of Clocks : 3

Frequency : 420 MHz

Tools Used : IC-Compiler, Star-RC, IC Validator, Prime Time. Role : To perform Sanity checks, Floor Plan, Power Plan, Placement, Timing Optimization, CTS, Routing, DRC, LVS. ACADEMIC PROJECT:

M.Tech Project:

Title: Smart Environment Monitoring System Using Internet of Things [IoT] for Smart City Description: This project develops an environmental monitoring system to measure the parameter variations in the area surroundings.

Results: Temperature, Humidity, Carbon dioxide and soil moisture parameter values are recorded and graphical representation also with LED is shown in the tool used. INTERNSHIP / CERTIFICATIONS:

Worked on Programmable logic controller [PLC] set up at Dayananda Sagar University, Bangalore, in collaboration with BOSCH Rexroth [July 2016- September 2016]. Description: Any real time examples were considered and the logic for the same was developed using ladder diagram and executed in the PLC.

Results: The simulation results were tested and verified with the manual entering of the input values.

CO-CURRICULAR ACTIVITIES:

Participated in IEEE-International Conference on Innovative Mechanism for industry applications[ICIMIA 2017] conducted by Dayananda Sagar College of Engineering, Bangalore, sponsored by IEEE Bangalore Section India from 21st to 23rd February 2017.

Attended workshop on “ASIC VERIFICATION” at MAVEN SILICON on 22nd April 2017.

Published paper on “Smart Environment Monitoring System using IoT” in Annual Technical Activities Contest-XPLORE 17 conducted by IEEE DSCE student branch with IEEE Bangalore section.

PERSONAL INFORMATION:

Father’s Name : SIDDESH NAIK

Date of Birth : 26/03/1992

Languages Known : English, Kannada, Hindi

Hobbies : Trekking, playing cricket and volleyball Address : Suragondanakoppa, Chinnikatte post

Honnali taluk, Davengere-577225

DECLARATION

I hereby declare that all the statements made above are correct to the best of my knowledge and belief.

Date:

Place:

Signature

[KISHORA NAIK S]

Contact this candidate