Industrial Training Project

CAREER OBJECTIVE

Seeking a challenging and enduring job in professional organization where my skills & abilities could be fully utilized to achieve organizational goals and professional growth.

ACADEMIC EDUCATION

B. Tech in Electronics & Communication Engineering from Nannapaneni Venkat Rao College of Engineering & Technology_Tenali,affiliated to JNTU-K with an aggregate 72.70 % in 2017.

Diploma from Govt. Polytechnic College for Women's affiliated to State Board of Technical Education_Palamaneru, Andhra Pradesh with an aggregate 77.8% in 2014.

10th from Z.P .High School affiliated to Board of Secondary Education_Chillamanuchenu, Andhra Pradesh with an aggregate 73% in 2011.

PROFESSIONAL TRAINING

An Industry Oriented Trainee in VLSI PHYSICAL DESIGN from Institute of Silicon Systems Pvt Ltd., Hyderabad since December 2017 to May 2018.

Course Outline:

VLSI Fundamentals, CMOS Basics, Digital Design Floor Planning, Power Planning, Placement and Routing, clock tree synthesis, static timing analysis timing optimization, cross talk analysis, IR Drop Analysis and Physical Verification.

Tools:

Experience in physical design of 130nm and 90nm technologies using Cadence tool

Cadence SOC Encounter –Floor Planning, Place & Route, and clock tree synthesis

Encounter Timing System –Static Timing Analysis and Cross-talk Analysis

RTL Compiler- Logic Synthesis

Virtuoso- Layout Designing

Assura – Physical Verification

TECHNICAL SKILLS

Operating system : Windows, Linux, Unix.

Languages : C, VHDL & TCL (Scripting Language Basics)

Software's : CST Studio

PROJECTS

PHYSICAL DESIGN:

Project 1:

Objective : Achieve less routing congestion and meet the timing.

Technology : TSMC 90nm

Tool : SOC Encounter

Macros / Gate Count : 12 / 303433

Metal Layer / Cell Count : 5 / 27318

Number of Clocks : 10

Frequency : Main clock with 200 MHz frequency.

Role: Performing Audit Checks, Floor Planning, Power Planning, Placement in Time Driven Mode, Congestion and Timing Analysis, Performing CTS, Detailed Routing and Timing Closure.

Project 2:

Objective : Achieve zero routing congestion and meet the timing.

Technology : TSMC 130nm

Tool : SOC Encounter

Macros / Gate Count : 12 / 116627

Metal Layers / Cell Count : 6 / 23509

Number of Clocks : 4

Frequency : Main Clock with 149.92 MHz frequency.

Role: Performing Audit Checks, Floor Planning, Power Planning, Placement in Time Driven Mode, Congestion and Timing Analysis, Performing CTS, Detailed Routing and Timing Closure.

LOGIC SYNTHESIS:

Project 1:

Objective : To achieve maximum frequencies by using M Vt for standard cells.

Technology : GF 65nm

Tool : RTL Compiler

Area Numbers : 6931 Sq mm(R Vt), 7566 Sq mm(H Vt), 6994 Sq mm(M Vt)

Power Numbers : 1.612mW (R Vt), 0.917mW (H Vt),1.648mW (M Vt).

Frequencies : 523.56 MHz (R Vt), 264.55 MHz (H Vt), 522.19MHz (M Vt).

Role: Writing SDC constraints and TCL scripts to meet required Area, Timing and Power constraints for a targeted technology.

Project 2:

Objective : To achieve minimum gate count by using Standard wire load models and zero wire load model.

Technology : GF 65nm

Tool : RTL Compiler

Number of Clocks : 2

Frequency : 200 MHz

Area Numbers : 315 Sq mm (ZWLM), 420 Sq mm (SWLM).

Gate Count : 139 (ZWLM), 140 (SWLM).

Role: Writing SDC constraints and TCL scripts to meet required Area, Timing and Power constraints for a targeted technology.

LAYOUT:

Project:

Objective : Designing Standard Cell Layouts

Technology : TSMC 130nm

Tools : Virtuoso, Assura.

Cells Designed : INVERTER, NAND, NOR, AND, OR, EXOR, EXNOR.

Role: Designing the Layout from the given Spice Net list and verifying the design DRC and LVS clean.

Challenges: Routing using only single metal layer (M1) and following half DRC rules.

ACADEMIC PROJECTS/OTHER EXPERIENCE

Done Project on "Compact UWB Antenna for Wireless Personal Area Networks" in B. Tech final year 2017.

Attending the one day National Seminar on “Soft Skills for Survival and Success in Career and Life” at Nannapaneni Venkat Rao College of Engineering and Technology in 2015.

Done industrial training for 6 months at “Amara Raja Electronics Pvt Ltd ” in diploma final year 2014.

Done Project on “Digital clock”in Diploma final year 2014.

PERSONAL DETAILS

Father’s name : P. Ramanaiah

Mother's name : P. Ramanamma

Date of birth : 18-05-1996

Language’s known : English, Telugu

Strengths : Self Motivated & Zeal to Learn.

Hobbies : cooking & I like to solve Sudoku puzzle.

Current Location : Hyderabad (Flexible to migrate)

Declaration:

I hereby declare that the above written particulars are true and correct to the best of my knowledge and belief.

DATE:

PLACE: (P. Rajamma)

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