| Resume alert | Resumes 61 - 70 of 130 |
Design Power
Portland, OR
... Key Strengths & Knowledge Analog Layouts • Chip Level Interface & Routing • Resistor/Diffusion Resistor Layout • Block Level Floor Planning Tape Out Process • PCELL Generation • Auto Router • Power Circuits • Power Bus Planning • CMOS/Bipolar ... - 2018 May 29
... Key Strengths & Knowledge Analog Layouts • Chip Level Interface & Routing • Resistor/Diffusion Resistor Layout • Block Level Floor Planning Tape Out Process • PCELL Generation • Auto Router • Power Circuits • Power Bus Planning • CMOS/Bipolar ... - 2018 May 29
Design Engineering
Portland, OR
... • Basic Operating System concepts, OOPS concepts, Shell Scripting (basics) • Scripting (Process Automation) experience using Python and coding experience in C, C++ and MATLAB • Standards/ Bus Protocols: USB, UART and basic conceptual knowledge of ... - 2018 Feb 12
... • Basic Operating System concepts, OOPS concepts, Shell Scripting (basics) • Scripting (Process Automation) experience using Python and coding experience in C, C++ and MATLAB • Standards/ Bus Protocols: USB, UART and basic conceptual knowledge of ... - 2018 Feb 12
C#.NET, HTML5, Java Script, AngularJS, VueJS
Portland, OR
... Used water fall model for the development Ensuring the quality of my project deliverables Used HART and Foundation Field Bus protocols to communicate with the flow, pressure and temperature devices used in manufacturing industries Documented and ... - 2018 Jan 23
... Used water fall model for the development Ensuring the quality of my project deliverables Used HART and Foundation Field Bus protocols to communicate with the flow, pressure and temperature devices used in manufacturing industries Documented and ... - 2018 Jan 23
CPU Performance/Design Verification Professional Experience
Portland, OR
... Generated a trace containing memory requests for different processors sharing bus. Design and Logic Synthesis of Synchronous FIFO (SystemVerilog/TCL/Synopsys DC/Perl) (Feb ’17-Mar ’17) Synthesized and generated netlist and run post synthesis ... - 2017 Nov 27
... Generated a trace containing memory requests for different processors sharing bus. Design and Logic Synthesis of Synchronous FIFO (SystemVerilog/TCL/Synopsys DC/Perl) (Feb ’17-Mar ’17) Synthesized and generated netlist and run post synthesis ... - 2017 Nov 27
Machine Operator Forklift, material specialist,Lab tech
Hillsboro, OR
... Jbox Soldering bus bar and Trimming. Working in Palletizer. Solar Panel inspection. Strapping and wrapping. Using Computer Paperless inventory (SAP). Reworks framing, jboxes and back sheet panel. Siemens (Under InSync Staffing) November 16, 2015 - ... - 2017 Sep 20
... Jbox Soldering bus bar and Trimming. Working in Palletizer. Solar Panel inspection. Strapping and wrapping. Using Computer Paperless inventory (SAP). Reworks framing, jboxes and back sheet panel. Siemens (Under InSync Staffing) November 16, 2015 - ... - 2017 Sep 20
Design Engineer
Beaverton, OR
... Design and Implementation of 16-bit RISC processor using VHDL, UNC Charlotte • Implemented a four-stage pipelined 16-bit processor with 8-bit wide data memory, 8-bit wide address bus, sixteen 8-bit registers and a non-preemptive interrupt handler. • ... - 2017 Jul 24
... Design and Implementation of 16-bit RISC processor using VHDL, UNC Charlotte • Implemented a four-stage pipelined 16-bit processor with 8-bit wide data memory, 8-bit wide address bus, sixteen 8-bit registers and a non-preemptive interrupt handler. • ... - 2017 Jul 24
Management Project
Portland, OR
... Advanced the use of service oriented architecture (SOA) for application development while incorporated the use of IBM’s Enterprise Services Bus (ESB). Directed the IT governance for the service delivery of $20 million of outsourced IBM ... - 2017 Jun 28
... Advanced the use of service oriented architecture (SOA) for application development while incorporated the use of IBM’s Enterprise Services Bus (ESB). Directed the IT governance for the service delivery of $20 million of outsourced IBM ... - 2017 Jun 28
Engineer Electrical
Beaverton, OR
... Title - Small Computer System Interface (SCSI) Bus Backplane Interface ADDITIONAL INFORMATION Licensed radio station operator in the US Amateur Radio Relay League (ARRL) call sign “Kilo, Delta Seven Hotel India Bravo” (KD7HIB). Station uses both ... - 2017 Apr 06
... Title - Small Computer System Interface (SCSI) Bus Backplane Interface ADDITIONAL INFORMATION Licensed radio station operator in the US Amateur Radio Relay League (ARRL) call sign “Kilo, Delta Seven Hotel India Bravo” (KD7HIB). Station uses both ... - 2017 Apr 06
Engineer Project
Portland, OR
... of data Sprint Optical Smartscope programming Creation of Process Validation Plans and Test Method Validation Protocols Field bus experience (Modbus, Profibus, TCP-IP) Specification, maintenance and troubleshooting of motor drives, stepper motors, ... - 2017 Mar 28
... of data Sprint Optical Smartscope programming Creation of Process Validation Plans and Test Method Validation Protocols Field bus experience (Modbus, Profibus, TCP-IP) Specification, maintenance and troubleshooting of motor drives, stepper motors, ... - 2017 Mar 28
Design Engineer Software
Portland, OR
... Experienced in signal integrity with high speed bus. Experienced in designing FPGA. Experienced in digital and analog signal processing. Strongly Understanding Microcontroller and creating code running on a naked MCU such as Arm STM32, C51series ... - 2016 Oct 08
... Experienced in signal integrity with high speed bus. Experienced in designing FPGA. Experienced in digital and analog signal processing. Strongly Understanding Microcontroller and creating code running on a naked MCU such as Arm STM32, C51series ... - 2016 Oct 08