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Design Power

Portland, Oregon, United States
May 29, 2018

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Page * of * 408-***-**** • • Portland, OR 97229


Diligent Professional with background of 14+ years in IC physical layout design in semiconductor industry. Offer deep expertise in custom/semi-custom layouts and verification/debugging (LVS, DRC, ERC, IR, EM, DFM). Highly efficient, collaborative, and thorough with ability to produce complex layouts/drawings from schematics and drive ongoing coordination with designers for seamless execution of deliverables/projects ahead of schedule and timely issue resolution. Experienced with deep submicron technologies along with memory, analog, RF, and mixed signal layout design techniques. Take initiative to learn and apply new methodologies, technologies, design rules, and tools in order to support changing priorities and key tasks.

Key Strengths & Knowledge

Analog Layouts • Chip Level Interface & Routing • Resistor/Diffusion Resistor Layout • Block Level Floor Planning Tape Out Process • PCELL Generation • Auto Router • Power Circuits • Power Bus Planning • CMOS/Bipolar Circuit Theory Chip Planning & Integration • Resistance Extraction • Decap Estimation • SRAM/DRAM Architecture • Memory Layouts Peripheral Devices (I/O Pads, ESD Structures) • Design Documentation • Device Matching & Isolation Techniques Overview of Technical Skills

• Cadence Virtuoso XL Calibre • Perl scripting • UNIX/Linux OS

ICV • Assura • Mentor Calibre • Apache RV tools • Realm • Synopsys ICV PROFESSIONAL EXPERIENCE

Mask Designer • Intel Feb 2012 - Feb 2018

Executing SoC version of DDR PHY Layouts in 10nm up to production quality (working on various verification flows)

Worked on Low-Jitter PLL blocks layout design in 14nm and 10nm and worked on verification flows.

Performed RF/analog and mixed signal CMOS circuits on FIVR PCH blocks in 14nm and worked on several verification flows to achieve the milestone

Provided design work on RF testrow structures for testchip upto TM1 in 14nm, 10nm and worked on LV flows and fixed all violations.

Worked on NAND Flash layouts as part of NSG.

Provided design work for various IPs and sub-blocks of PLL, DDR, SerDes PHY layout and other custom and semi- custom layouts as part of Intel Custom Foundry’s Analog IP Design team.

Participated in ECOs related to timing and RV on various blocks.

Held role in developing customized standard cell library for PLL.

Completed all sub-blocks using analog layout methodologies, Intel-specific FINFET techniques, and PG grid integration (TM1 and C4bump).

Executed DRCD assessment on DDR macros w.r.t. new ICV runsets and new templates from TD, which included coordinating with DE/DA teams for timely resolution of issues for ECOs and tool/flow issues; facilitated seamless sub- block integration with LEF generation and worked closely with top-level block owner.

Worked on various process nodes 1271.2, 1271.6 (22nm), 1273.6 (14nm), and 1275.6 (10nm).

Performed LVS, DRCD, Density, IPALL, HV, and ESD layout verification checks and resolved all issues.

Facilitated benchmarking studies between ICV and Calibre for runtimes, error types, and error counts. Recent Highlights:

Received various recognitions for performance and consistent on-time or ahead of schedule delivery.

Continuously engaged to realign delayed initiatives and provided reliable support and assistance to more senior-level engineers and managers in delivering on projects ahead of time. UMADEVI CHALLA 408-***-**** • • Page 2 of 3

Contributed to addressing audit issues associated with block verification based on consistent record of accuracy, providing thorough review and error cleanup that resulted in taking on additional assignments.

Proved vital to critical issue resolution and fixes associated with cell sizes that resulted from accommodation of block changes following IP release, completing task on time.

Involved in knowledge sharing among team based on in-depth experience with navigating verification tools.

Alleviated workload for design engineers during peak period by learning and using key tool to find and fix violations vs. sending request to engineers; recognized by manager for taking initiative. Tools: Cadence VXL, Genesys Layout Tool, OA Scripting, Cadence Skill for PCELL Generation & Bindkey Settings Mask Designer II • Edison Semiconductor (subsidiary of Elpida, now owned by Micron) 2007-2009

Instrumental in various analog IPs of 128MBx32 DDR1 DRAM designed in 70nm and 50nm CMOS process for digital consumer applications as well as 256MB DDR1 DRAM in 90nm; involved in floor plan/architecture discussions.

Collaborated with IC design team, coordinated with designers in support of iterations, documented specifications and prepared design documentation, provided technical guidance to junior designers, and delivered tape out support.

Designed layouts for general analog and RF circuits as well as worked on physical layout design for power circuits, completing efforts ahead of schedule; handled floor planning, layout modules, and full chip integration.

Worked on chip/top level routing, chip-level interface, block floor-planning and placement, power bus planning, resistance extraction, decap estimation/placement, and layout schedule estimates.

Contributed to noise reduction and critical issue resolution by analyzing fluctuations and providing recommendations.

Completed LVS, DRC, ERC, IR, EM, and DFM physical verification.

Determined area feasibility and drove optimization of areas and functionality.

Contributed to memory power grid, resistance extraction, and power grid improvement.

Involved in defining new methodology with latest technology and refining current layout workflows.

Provided custom layout for complex blocks in line with all design specifications.

Managed analog circuit specific layout issues and techniques, including matching, crosstalk isolation, reliability, and DFM. Tools: Cadence Virtuoso XL, Calibre for Physical Verification, Star-RCXT for RC Extraction, Realm for IR Drop Analysis, Perl Scripting, UNIX/Linux, Skill Programming

Mask Designer I • TES Technologies 2006-2007

Created DAC and PLL layouts in TSMC 0.13 um technology in coordination with IC design team, focusing primarily on preparing schematics and writing CDL code; performed cell-level verification and parasitic extraction.

Worked on layouts for analog and digital circuits, hierarchical layouts, power bussing, documentation, Skill programming, layout schedule estimation, and schematic entry based on spice netlists/CDL.

Conducted LVS, DRC, ERC, and DFM checks and provided error resolution; adhered to checklists for design consistency. Tools: Tanner L-Edit, Cadence Virtuoso, Assura, Calibre for Physical Verification, Star-RCXT for RC Extraction, Linux Mask Designer • Inter Weave Technologies 1998-2002

Designed layouts for address decoders, I/O column muxes, and memory control logic as part of standard cell and memory layouts in 0.25 um technology; worked closely with IC design team and created documentation.

Prepared multi-dimensional layouts and detailed drawings of semiconductor devices based on schematics and geometry provided by circuit designer.

Completed checklists to ensure design consistency and handled DRC, LVS, ERC, DFM checks. Tools: Dracula DRC/LVS, Dracula ERC/DFM, Magic Layout Tools, Tanner L-Edit, Cadence Virtuoso, Linux Mask Designer • ITU 1998

Contributed to full custom layout of a simplified SRAM (256X8) in cell, block, and full chip-level design for a 0.6 um double metal CMOS process, including decoders, registers, data I/O buffers, control circuits, and peripheral devices. UMADEVI CHALLA 408-***-**** • • Page 3 of 3

Worked on DRC, LVS, and DFM in addition to global routing for power bus distribution and signal bus connections. Tools: Cadence Layout Editor; Cadence Verification Tools; Dracula LVS; DIVA DRC EDUCATION & TRAINING

Place & Route Training TTM [Bangalore, India]

Certificate of IC Mask Design International Technological University [Santa Clara, CA] Intro to UNIX Course & Programming in Perl Course De Anza College [Cupertino, CA] Bachelor of Science Andhra University [Visakhapatnam, India]

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