| Resume alert | Resumes 71 - 80 of 311 |
Project Data
DL, India
... VLSI Design Banasthali University 2014-2016 79.06(upto 2nd sem) B.Tech. Electronics and Communication Rajasthan Technical University 2010-2014 73.10 Senior secondary Physics, Chemistry, Math RBSE Board 2010 70.77 secondary All Subject RBSE Board ... - 2017 Jun 13
... VLSI Design Banasthali University 2014-2016 79.06(upto 2nd sem) B.Tech. Electronics and Communication Rajasthan Technical University 2010-2014 73.10 Senior secondary Physics, Chemistry, Math RBSE Board 2010 70.77 secondary All Subject RBSE Board ... - 2017 Jun 13
Design Engineering
Faridabad, HR, India
... TEACHING AREA OF INTEREST Control System, Network Analysis & Synthesis, Signals and Systems,Electronics Circuit, Integrated Circuit, VLSI Design, Analog & Digital electronics, Electronic devices, Sensor & Instrumentation, Introduction to electric ... - 2017 Feb 11
... TEACHING AREA OF INTEREST Control System, Network Analysis & Synthesis, Signals and Systems,Electronics Circuit, Integrated Circuit, VLSI Design, Analog & Digital electronics, Electronic devices, Sensor & Instrumentation, Introduction to electric ... - 2017 Feb 11
Design System
Faridabad, HR, 121006, India
... Languages : TCL/TK, Bash Scripting Language, MATLAB, Verilog, System Verilog, C/C++ Area of Interest : VLSI Design and verification. PROJECTS Title: I2C Protocol Designing (October 2016- present) Tools/Technology Used: Modelsim SE, Verilog My Role: ... - 2017 Jan 22
... Languages : TCL/TK, Bash Scripting Language, MATLAB, Verilog, System Verilog, C/C++ Area of Interest : VLSI Design and verification. PROJECTS Title: I2C Protocol Designing (October 2016- present) Tools/Technology Used: Modelsim SE, Verilog My Role: ... - 2017 Jan 22
Engineer Data
Gurugram, HR, India
... Detailed VLSI Work Experience: ASIC IP Verification Engineer at Achala technologies Pune, January 2013 – December 2013 Worked for the verification of Ethernet protocol based MAC products (1G, 10G, 100G). Responsible for test writing for these ... - 2016 Dec 06
... Detailed VLSI Work Experience: ASIC IP Verification Engineer at Achala technologies Pune, January 2013 – December 2013 Worked for the verification of Ethernet protocol based MAC products (1G, 10G, 100G). Responsible for test writing for these ... - 2016 Dec 06
Power Plant Engineering
Ghaziabad, UP, 201001, India
... Participated in workshop of “digital design system using FPGA (VLSI Frontend) and ASIC Design and Layout (VLSI Backend). Prize in All India Essay Writing Event 2011 organised by Shri Ram Chandra Mission and United Nations Information Centre for ... - 2016 Oct 07
... Participated in workshop of “digital design system using FPGA (VLSI Frontend) and ASIC Design and Layout (VLSI Backend). Prize in All India Essay Writing Event 2011 organised by Shri Ram Chandra Mission and United Nations Information Centre for ... - 2016 Oct 07
embedded / FPGA design
DL, India
... Worked as VLSI intern at Embedded Technologies from 12’Jan 2016 to 13’aug 2016. Presently working at Embedded Technologies as an Embedded/FPGA Research Engineer from 27’Aug 2016 till date. ACADEMIC QUALIFICATIONS: Examination Discipline Institute ... - 2016 Oct 06
... Worked as VLSI intern at Embedded Technologies from 12’Jan 2016 to 13’aug 2016. Presently working at Embedded Technologies as an Embedded/FPGA Research Engineer from 27’Aug 2016 till date. ACADEMIC QUALIFICATIONS: Examination Discipline Institute ... - 2016 Oct 06
Data System
201301, India
... EDUCATIONAL CREDENTIALS 2015 Master of Technology (VLSI DESIGN) from S.R.M UNIV, GHAZIABAD with 8.5 CGPA. 2012 2006 2004 Bachelor of Technology (Electronics & Comm. Engg) from R.B.I.T (U.P.T.U) 70 %. Intermediate from G.S inter college with 70% X ... - 2016 Sep 26
... EDUCATIONAL CREDENTIALS 2015 Master of Technology (VLSI DESIGN) from S.R.M UNIV, GHAZIABAD with 8.5 CGPA. 2012 2006 2004 Bachelor of Technology (Electronics & Comm. Engg) from R.B.I.T (U.P.T.U) 70 %. Intermediate from G.S inter college with 70% X ... - 2016 Sep 26
Skills: bash, verilog, perl, python, tcl, cshell
New Delhi, DL, 110001, India
... (VLSI Design) C-DAC Noida (GGSIPU) 78.93% 2011 B.Tech. (Electronics & Telecomm.) MGM COET, Noida 70.9% 2007 XII (CBSE) DAV Public School, Brij Vihar 71.6% 2005 X (CBSE) DAV Public School, Brij Vihar 78.4% - 2016 Sep 19
... (VLSI Design) C-DAC Noida (GGSIPU) 78.93% 2011 B.Tech. (Electronics & Telecomm.) MGM COET, Noida 70.9% 2007 XII (CBSE) DAV Public School, Brij Vihar 71.6% 2005 X (CBSE) DAV Public School, Brij Vihar 78.4% - 2016 Sep 19
Industrial Training Project
201301, India
... ACHIVMENTS Two week industrial training on VLSI PERSONAL SKILLS •Confidence and Self Motivated. •Hardworking and sincere. •Ability to adopt quickly as per requirements. PERSONAL INFORMATION •Name : Neha Kumari •Father's Name :Shiv prasad singh •Date ... - 2016 Sep 18
... ACHIVMENTS Two week industrial training on VLSI PERSONAL SKILLS •Confidence and Self Motivated. •Hardworking and sincere. •Ability to adopt quickly as per requirements. PERSONAL INFORMATION •Name : Neha Kumari •Father's Name :Shiv prasad singh •Date ... - 2016 Sep 18
plc automation engineer, electronic &communication
New Delhi, DL, India
... : Window 2007,Window p, Window 7 • HARDWARE PROGRAMIG :VHDL • MICRCOPROCESSOR & MICROCONTROLAR PROGRAMMING :8085, 8086, 8051 • Pcb design and pcb mounting & testing,Cmos VLSI Design,bts install WORKING EXPERIENCE:- B • Vidya Electrotech Pvt. ... - 2016 Aug 10
... : Window 2007,Window p, Window 7 • HARDWARE PROGRAMIG :VHDL • MICRCOPROCESSOR & MICROCONTROLAR PROGRAMMING :8085, 8086, 8051 • Pcb design and pcb mounting & testing,Cmos VLSI Design,bts install WORKING EXPERIENCE:- B • Vidya Electrotech Pvt. ... - 2016 Aug 10