Design Engineering

SUMAN KUMAR

B-***/*, Lohia Nagar

Ghaziabad, U.P-201001

Phone: +919*********

+917*********

E-mail: *******.****@*****.***

OBJECTIVE

To grow in pace with recent developments and become a pioneer in organization and technical field. EXPERIENCE

• Currently working as Assistant professor in ECE Branch in Acme college of Engineering, Murad nagar (U.P) since 17th Aug 2015.

• Previously worked as Asst.Proff. in Dr. K. N Modi Institute of Engineering and Technology,Modi nagar U.P from Aug 2011 to Aug 2014.

• Teaching Faculty of Easy Way Tutorials (1 year,private coaching) during B.E.

• Lab Assistanceship in NIT Rourkela( 1 Year) during M.Tech . TEACHING AREA OF INTEREST

Control System, Network Analysis & Synthesis, Signals and Systems,Electronics Circuit, Integrated Circuit, VLSI Design, Analog & Digital electronics, Electronic devices, Sensor & Instrumentation, Introduction to electric drive. SYNOPSIS

• M.TECH in VLSI Design & Embedded System from NIT Rourkela.

• Sound knowledge of VLSI Design Tools and Techniques.

• Detail-oriented with an analytical bent of mind and positive attitude.

• Capable at grasping new technical concepts quickly and utilising it in a productive manner.

• An out of box thinker with excellent team management/building & motivation skills. ACADEMIC QUALIFICATION

Course

University/Board College/School Year of Passing Aggregate MTECH-

VLSI Design &

Embedded

system(ec)

National institute of

technology

National institute of

technology, Rourkela

2011 7.69(CGPA)

B.E(Electronics

& tele-comm)

AMIETE

University

IETE, New Delhi 2009 7.14(CGPA)

Intermediate

Board of

Intermediate

Marwari college, Ranchi

(Jharkhand)

2004 56%

Matric CBSE GBRC, Bodhgaya (Bihar) 2002 76.6%

PROJECT DETAIL

Project Title: Simulation on Trapping Effect of 4H-SiC MESFETs Description: 4H-SiC MESFET technology is used for high power application due to its wide bandgap and high thermal conductivity. But due to influence of surface trap and buffer trap in semi insulating substrate many electron and hole are trapped in substrate from channel. Due to which it reduces the power and current. So different growth technique like PVT (physical vapor transport),HTCVD(High temperature chemical vapor deposition) is used to improve the power and current by making semi-insulating 4H-SiC. Simulation of I-V characteristics have been done by taking both with and without trap model, self heating effect, field dependent mobility and we compared all our result with each other.

Interface of ADC and DAC with FPGA.

Description: Analog signal is converted in Digital signal and vice-versa using FPGA (Field programmable gate array) kit. Here we dumped the signal by giving location of FPGA kit in Xilinx software. TECHNICAL SKILLS

VLSI/ASIC Design and Verification:

• RTL Coding in Verilog and VHDL.

• Behavioral model for verification.

• Syntehsis.

• RTL/Pre-Layout/Post-Layout netlist verification.

• Formal Verification: RTL, netlist and at various stages of implementation.

• Porting of the Design from FPGA to ASIC.

FPGA Design:

• Systemetic and Qualitative approach for FPGA implementatons.

• Design and Implementation of IP blocks.

• Integration of IP blocks and system level functional simulation.

• Mapping Designs to target FPGA and physical synthesis.

• Expertise in emulation environment for multi-million gate System On Chip designs.

• Innovative target board design techniques to enable emulation system seamless interfacing with real time test equipments and debugger

Cadence Design

• System Design and verification

• Functional Verification

• Logic Design

• Digital Implementation

• Custom IC Design

• RF Design

• PCB Design

SOFTWARE TOOL

Xilinx tool

Matlab

Cadence

SCHOLASTIC ACHIEVEMENT

Qualified GATE 2009 with 95.69 percentile

PUBLISHED JOURNAL

Suman Kumar, Neti V.L.Narsimha Murty, "An Improved I-V model of 4H-SiC MESFETs with multiple deep level traps (DLT)", ISST Journal of Electrical & Electronics Engineering, Vol.3 No.2, pp.1-6,2012. CONFERENCES

Attended the International conferences on Electronic System (ICES 2011) in NIT Rourkela. PERSONAL DETAIL

Name : Suman Kumar

Father's Name : Suresh Prasad

Mother's Name : Alpana Devi

Date of Birth : 15 may 1988

Languages known : English, Hindi

E-mail Id : *******.****@*****.***

Permanent Address : Kamala Bhawan,

Opposite to Jama Masjid

Pulpar, Bihar Sharif

Nalanda, Bihar-803101

I hereby information furnished above is true to the best of my knowledge. Date: ( Suman kumar)

Place: Ghaziabad

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