CAREER OBJECTIVE

Seeking a challenging position to utilize my skills and creativity in the field of Electronic System design which will offers professional growth while being innovative and resourceful

ACADEMIC QUALIFICATION

Qualification

Institute

Board/University

Time Span

System Verilog

DKOP LABS PVT LTD,NOIDA

-

Aug 2015-Jan 2016

B. Tech. (ECE)

MANAV RACHNA COLLEGE OF ENGINEERING,FARIDABAD

MDU,ROHAK

2010-2014

12th (AISSCE)

DELHI PUBLIC SCHOOL, FARIDABAD

CBSE

2010

10th

DELHI PUBLIC SCHOOL, FARIDABAD

CBSE

2008

Qualified GATE 2016

EXPERIENCE

•Position: Assistant Manager 1.10 year (February 2015 – Present)

Company: Digital Control System, Faridabad

Manage two sewage disposals of MCF having 6 motor pumps of 100 HP at each disposal,

Manage and motivate operative and maintenance staff.

Monitor, measure and report performance and maintenance of sewage disposals.

Ensure that Health and Safety rules and regulations are adhered and all matters relating to this are dealt with using the resources within the company in line with the companies Health and Safety policy.

Maintaining high level of timekeeping.

•Position: Product validation Intern 6 month (August 2014 – January 2015)

Company: Calypto Design System pvt ltd, Noida

Projects:-

Title: PowerPro Validation

Tools/Technology Used: Powerpro, Verilog, VHDL, TCL/TK, System Verilog

My Role:

Test logical correctness of gating logic inserted by PowerPro in the customer design.

Analyzed customer bugs, front-end bugs and create unit-testcases using Verilog, VHDL, system Verilog, TCL/TK to reproduce same issue which helped developer to resolve bugs quickly.

Initiated on a project to show clock tree structure pictorially using TCL/TK. It can be helpful

•To visualize information present in spef

•Understand difference in amount of delay at different routes towards different flops.

INTERNSHIP DURING GRADUATION

•Position: Intern 5 month (January – May 2014)

Company: Truechip Solution pvt ltd, Noida

Projects:-

Title: Automation in Verification IPs on System Verilog

Tools/Technology Used: Tcl/Tk, Verilog

My Role:

Initiated a project on “Automation in Verification IPs on System Verilog“ for in-house colleagues to improve the quality standards and accelerate verification cycle time by creating Graphic User Interface (GUI) using Tcl/Tk and created some Verilog codes to check the functionality of Graphical User Interface.

Title: Universal Shift Register Using Verilog And TCL/TK

Tools/Technology: Verilog, Tcl/Tk

My Role:

Created logic circuit layout to depict 4-bit Universal shift register using TCL/TK and a verilog design code of 4-bit universal shift register to examine shifting in output and intermediate signal values.

Tcl/Tk projects

Scientific Calculator, Tic Tac Toe Game, File Browser (using only listbox).

TECHNICAL SKILLS

Software tools : MATLAB R2013a, Xilinx ISE, ModelSim, QuestaSim, kiel., MPlab, PSPICE.

Languages : TCL/TK, Bash Scripting Language, MATLAB, Verilog, System Verilog, C/C++

Area of Interest : VLSI Design and verification.

PROJECTS

Title: I2C Protocol Designing (October 2016- present) Tools/Technology Used: Modelsim SE, Verilog

My Role:

Designed FSM and wrote Verilog code for Master. Writing verilog code for slave, address latch.

Title: AMBA AHB 2.0 Protocol Designing (March –August 2016)

Tools/Technology Used: ModelSim SE, Verilog

My Role:

Designed FSM and wrote Verilog code for Master, slave, Arbiter.

Title: LC3 Protocol(non-pipelined) verification (December 2015 – January 2016)

Tools/Technology Used: QuestaSim 10.2, System Verilog

My Role:

Verified each block i.e Fetch, Decoder, Execute, Controller, then verified full LC3 protocol connecting all block together using interface, Queue/mailbox.

Title: Universal Asynchronous Receiver/Transmitter(UART) Designing (September –October 2015)

Tools/Technology Used: Modelsim SE, Verilog

My Role:

Designed FSM, wrote Verilog code and made testbench for UART.

Title: AMBA-APB 2.0 Protocol Designing (October -November 2015)

Tools/Technology Used: Modelsim SE, Verilog

My Role:

Designed FSM, wrote Verilog for slaves, master(bridge), with address latch and decoder to generate PSEL signal of AMBA-APB protocol and created testbench to verify the design.

ACADEMIC PROJECTS

Digital thermometer

Made a PCB hardware design and wrote a code on MPlab software for a digital thermometer which could sense the heat with the help of heat sensor and displayed temperature reading on LCD screen. Hex code generated using MPlab was burnt on PIC microcontroller.

Remote controlled robot car

Made a PCB hardware design and wrote code on Keil software for wireless remote controlled robo-car which had had the functionality to move forward, backward, right and left. The Hex code generated using Keil was burnt on microcontroller 8051. RF transmitter and receiver were used to send and receive signals.

Function Generator: -

Made a PCB hardware design for variable function generator with output waveforms of sine, square and triangular in frequency range of 1-10 Khz.

5v dc power supply (without using diodes)

Made a PCB hardware design for 5v dc Power supply.

ACHIEVEMENTS

Awarded appreciation letter from my professor in control systems for excellent performance in a project titled “MATLAB IMPLIMENTATION OF 1ST AND 2ND ORDER CONTROL SYSTEM” during 6th semester session.

Awarded certificate for ethical hacking program (level 1).

Awarded Medal for excellent academic performance in school, 12th class.

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