Wasim Nasir Shaikh

***, **** ****, **** ******.

Contact:997-***-****,acxr7j@r.postjobfree.com

WORK EXPERIENCE:

April 2013 – Dec 2013 Achala Technologies.

Worked as ASIC IP Verification Engineer at Achala technologies Pune, January 2013 – December 2013.

Experience in UVM-based verification for Ethernet protocol.

Experience in writing test-cases and debugging.

Worked on UVM- environment development of sgmii & qsgmii PCS.

Experience in coverage implementation and coverage analysis.

July 2014 – Dec 2015 Opel Telecom Inc.

Worked as Service Engineer.

Work involved installation of attendance machine and EPABX system.

Servicing of these products, and resolving customer queries of these products was main concern.

Also was responsible for marketing of these products, Generating new customer for company was added responsibility.

Dec 2015 – Till Date Vedang Cellular services pvt ltd.

Working as NPO Coordinator at Nokia Solutions Networks Pune for Maharashtra and Goa circle.

Job involves coordinating between different Vendors for carrying the project management activities regularly.

Detailed VLSI Work Experience:

ASIC IP Verification Engineer at Achala technologies Pune, January 2013 – December 2013

Worked for the verification of Ethernet protocol based MAC products (1G, 10G, 100G).

Responsible for test writing for these products.

Completed debugging of these tests so as to meet the required specification.

Responsible for complete environment bring up for low speed pcs.

Implemented UVM based environment and test-bench for sgmii and qsgmii pcs.

Implemented UVM based scoreboards as per standard so as to verify the functionality of design.

Implemented coverage for sgmii and qsgmii pcs.

Conducted periodic code and functional coverage analysis to compare against coverage goals, and write/modify tests accordingly.

Maintain Documentation of the work done, this included coverage plans, test plans and test descriptions.

Independent VLSI work experience.

Hardware Implementation of CAN protocol. (Oct-2014 – Apr-2015) & (Aug-2015 – Nov - 2015)

Worked on Hardware implementation of CAN protocol which was implemented as PG-diploma project. The Core Design was extended to support new interface.

Work done included configuring the FPGA Virtex-5; Interfacing it with CAN PHY.

Also debugged design working on FPGA by using Chip-scope analyzer.

The CAN PHY (PCA-82C251) is selected to match the CAN speed of 1Mbps.

UVM Based Verification Environment for Async-fifo. (May - 2016 – July 2016)

The work involved implementation of Async-fifo on verilog platform and For verification of design UVM based environment is implemented from scratch.

Complete environment, Scoreboard and Coverage model is implemented.

Design of SPI protocol based IP and UVM based verification environment.(Aug 2016 –Till Now)

The Work involves implementation of Verilog based design of SPI IP.

ACADEMICS :

Completed Post-Graduate Diploma in VLSI Design (14th Feb, 2012 – 28th July, 2012) from C-DAC’s Advanced Computing Training School, Pune.

Completed Bachelor of Engineering (Pune University), May 2011,Pune

Electronics & Tele-communication.

Marathwada Mitra Mandal’s College of engineering.

TECHNICAL SKILLS:

HardwareDescription Languages:

Verification methodology:

Software Languages:

Operating System:

EDA Tools:

Verilog, System Verilog, VHDL.

UVM.

C, CPP(Basic).

Windows, Linux.

Xilinx 12.2, Incisive (NCSim), QuestaSim, MATLAB(Basic).

ACADEMIC PROJECT:

Title

Platform

Description

IMPLEMENTATION OF CONTROLLER AREA NETWORK (CAN) PROTOCOL CONTROLLER. (CDAC)

VERILOG.

Controller Area Network (CAN) is two-wired, half duplex, Low-speed network system. It is a multi-master serial bus that uses broadcast messaging to transmit to all CAN nodes. The controller designed functions as the interface between a host and the actual CAN bus. The RTL based design was implemented using Verilog HDL and verified using Verilog based Test-bench.

Title

Duration

Platform

Description

AN FPGA IMPLEMENTATION OF ADAPTIVE FILTER.

12 Months

VHDL, MATLAB.

Adaptive filters learn the statistics of their operating environment and continually adjust their parameters accordingly. An adaptive filter is a filter that self-adjusts its transfer function. It is first implemented on MATLAB, after getting correct results RTL implementation is done using VHDL. Physical realization of algorithm was done using XILINX 10.1 synthesis tool and verified using XILINX SPARTAN 3 FPGA.

Title

Duration

Description

GENERATION OF DIRECT SEQUENCE SPREAD SPECTRUM.

6 months.

The system accepts the 8 bit data from user; Encodes it and transmits. At the receiving end the data received is decoded and original data is recovered. For encoding of data it uses PN sequence which is generated using 16 D flip-flop. This generated PN sequence is added to data so that data looks to be noisy signal. For decoding again the same PN sequence is to be added to receiving data so as to get original data.

Extracurricular:

Worked in college organization committee and assisted in conducting different technical and cultural events.

PERSONAL INFORMATION:

Date of birth:

Gender :

Nationality:

Languages Known:

29th Nov 1989.

Male.

Indian.

English, Hindi and Marathi.

I hereby declare that above information is true to the best of my knowledge.

PLACE: Pune. (Wasim Nasir Shaikh.)

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