| Resume alert | Resumes 11 - 20 of 507 |
Layout Designer Senior Staff Engineer
San Jose, CA
... Prize -Ultra Low Power 1M SRAM Development Oct 1986 Samsung Group Gold Technical Prize -Ultra Low Power 256K SRAM Development Tools: - Cadence Virtuoso(with Calibre) Education: Mar 1980 ~ Feb 1984 Sogang University (Seoul, Korea) BS (EE & Math) - Jan 27
... Prize -Ultra Low Power 1M SRAM Development Oct 1986 Samsung Group Gold Technical Prize -Ultra Low Power 256K SRAM Development Tools: - Cadence Virtuoso(with Calibre) Education: Mar 1980 ~ Feb 1984 Sogang University (Seoul, Korea) BS (EE & Math) - Jan 27
Electrical Engineering System Design
San Jose, CA, 95126
... TECHNICAL SKILLS Programming Language: C, Python, Verilog, C++ Operating System: Windows & Linux Software Tools: Cadence Virtuoso, Keil Micro vision, Xilinx Design Suite, Model Sim, Intel Quartus Prime, Prime Time, Design Vision, Xilinx Vivado. ... - Jan 10
... TECHNICAL SKILLS Programming Language: C, Python, Verilog, C++ Operating System: Windows & Linux Software Tools: Cadence Virtuoso, Keil Micro vision, Xilinx Design Suite, Model Sim, Intel Quartus Prime, Prime Time, Design Vision, Xilinx Vivado. ... - Jan 10
Systems Engineer Project Management
Fremont, CA
... 8 Years’ experience in Cadence Concept HDL, Allegro & OrCAD. More recent Version’s 16.6 - 18.6 7+ Years’ experience Mentor Expedition. More recent Version’s 2.8 – 2.11 2 Years’ experience Zuken. 2 Years’ experience Pads PCB. 2 Years’ experience ... - Jan 09
... 8 Years’ experience in Cadence Concept HDL, Allegro & OrCAD. More recent Version’s 16.6 - 18.6 7+ Years’ experience Mentor Expedition. More recent Version’s 2.8 – 2.11 2 Years’ experience Zuken. 2 Years’ experience Pads PCB. 2 Years’ experience ... - Jan 09
Customer Service Senior Technical
Fremont, CA
... •Aligned with enterprise-wide Agile teams, driving Agile cadence and fostering collaboration. •Conducted show-and-tell sessions to articulate solutions to IT/business stakeholders. Graduate Assistantship, Bradley University 07/2022 – 05/2023 Peoria, ... - 2023 Dec 27
... •Aligned with enterprise-wide Agile teams, driving Agile cadence and fostering collaboration. •Conducted show-and-tell sessions to articulate solutions to IT/business stakeholders. Graduate Assistantship, Bradley University 07/2022 – 05/2023 Peoria, ... - 2023 Dec 27
Software Engineer C C++
Milpitas, CA
... multithreaded applications(C++17, C++14, C++11, C++98) on Linux/FreeBSD 15+ years Recently Used Zoom Video Communications, Cadence, Netapp, Isilon, Hammer Space C Programming 20+ years 2021 Netapp, Atlantis Computing, EMC, IBM, Other consulting ... - 2023 Nov 25
... multithreaded applications(C++17, C++14, C++11, C++98) on Linux/FreeBSD 15+ years Recently Used Zoom Video Communications, Cadence, Netapp, Isilon, Hammer Space C Programming 20+ years 2021 Netapp, Atlantis Computing, EMC, IBM, Other consulting ... - 2023 Nov 25
Scrum Master Program Management
Pleasanton, CA
... • Eliminated development bottlenecks and improved product releases by introducing SAFe methodology, conducting organization-wide training, and establishing a quarterly release planning cadence across all three verticals. • Managed ISO27001 and SOP2 ... - 2023 Nov 15
... • Eliminated development bottlenecks and improved product releases by introducing SAFe methodology, conducting organization-wide training, and establishing a quarterly release planning cadence across all three verticals. • Managed ISO27001 and SOP2 ... - 2023 Nov 15
Design Engineer Rtl
San Jose, CA, 95118
... Used VIPs from Cadence, Synopsys Resolved LP related Multi-mode, Multi-corner MMMC, STA timing corners and PVT issues. Transformed verification components from OVM/SystemVerilog and VMM to UVM Developed UVM infrastructure for block and partition ... - 2023 Oct 31
... Used VIPs from Cadence, Synopsys Resolved LP related Multi-mode, Multi-corner MMMC, STA timing corners and PVT issues. Transformed verification components from OVM/SystemVerilog and VMM to UVM Developed UVM infrastructure for block and partition ... - 2023 Oct 31
Layout Designer Design
San Jose, CA
... Specialist of Millimeter wave performance circuit optimization with EMX and PEX · Excellent knowledge of Analog supply techniques, creative executions and technology/software · Familiar with CAD: Cadence, ADS, ASW from schematics simulation and ... - 2023 Oct 23
... Specialist of Millimeter wave performance circuit optimization with EMX and PEX · Excellent knowledge of Analog supply techniques, creative executions and technology/software · Familiar with CAD: Cadence, ADS, ASW from schematics simulation and ... - 2023 Oct 23
Business Development Project Management
San Carlos, CA, 94070
... • Cadence & Sales Playbook Development: Revamped Salesloft cadences and maintained comprehensive BDR playbook for consistent onboarding and improved lead conversion rates. • Marketing Integration: Collaborated closely with Marketing team to align ... - 2023 Oct 04
... • Cadence & Sales Playbook Development: Revamped Salesloft cadences and maintained comprehensive BDR playbook for consistent onboarding and improved lead conversion rates. • Marketing Integration: Collaborated closely with Marketing team to align ... - 2023 Oct 04
C++ Verification Engineer
San Mateo, CA
... Participated in the training of Metric Driven Verification given by Cadence. Experience in silicon bring-up and debugging. 5+ years of experience in RTL design and Verification. 3+ years of Pre-SI verification work using a validation methodology UVM ... - 2023 Sep 21
... Participated in the training of Metric Driven Verification given by Cadence. Experience in silicon bring-up and debugging. 5+ years of experience in RTL design and Verification. 3+ years of Pre-SI verification work using a validation methodology UVM ... - 2023 Sep 21