| Resume alert | Resumes 41 - 50 of 128 |
Cisco Certified Network Associate
Los Angeles, CA
... Knowledge of Cisco Packet Tracer, LINUX, Verilog, Xilinx ISE, MATLAB, MAXWELL 14.0, ANSYS, OPNET, Computer technologies, applications & languages such as C, Eclipse, Code Blocks. Flair of utilizing modern principles, techniques and methods in ... - 2017 Jul 12
... Knowledge of Cisco Packet Tracer, LINUX, Verilog, Xilinx ISE, MATLAB, MAXWELL 14.0, ANSYS, OPNET, Computer technologies, applications & languages such as C, Eclipse, Code Blocks. Flair of utilizing modern principles, techniques and methods in ... - 2017 Jul 12
CCNA
Los Angeles, CA
... SKILLS: ● Programing Language: Socket Programming with Python, C++, C, Verilog, VHDL, Object Oriented Programming, CLI. ● Software Tools: GNS3, Putty, Microsoft Visio, Solar Winds Management, OPNET, MATLAB, WANDL, Xilinx XSE, LABVIEW, Keil, PSpice. ... - 2017 Jul 03
... SKILLS: ● Programing Language: Socket Programming with Python, C++, C, Verilog, VHDL, Object Oriented Programming, CLI. ● Software Tools: GNS3, Putty, Microsoft Visio, Solar Winds Management, OPNET, MATLAB, WANDL, Xilinx XSE, LABVIEW, Keil, PSpice. ... - 2017 Jul 03
Computer Science Data
Thousand Oaks, CA
... { Translated some design specifications from English to Chinese { Wrote Verilog HDL testbenches on existing designs { Redesigned errorous modules Honors & Awards May, 2010– July, 2010 Selected Student of Chong Chi College as a summer school student ... - 2017 Jun 19
... { Translated some design specifications from English to Chinese { Wrote Verilog HDL testbenches on existing designs { Redesigned errorous modules Honors & Awards May, 2010– July, 2010 Selected Student of Chong Chi College as a summer school student ... - 2017 Jun 19
Design Electrical Engineering
Los Angeles, CA
... Circuit Design (EE477) Project Experience DDR3 Controller Design (Verilog, NCSim, DC Compiler, Prime Time, Cadence Encounter) November 2016 Designed a DDR3 controller in Verilog RTL supporting Scalar, Block, Atomic Read/Write and refresh operations; ... - 2017 Feb 10
... Circuit Design (EE477) Project Experience DDR3 Controller Design (Verilog, NCSim, DC Compiler, Prime Time, Cadence Encounter) November 2016 Designed a DDR3 controller in Verilog RTL supporting Scalar, Block, Atomic Read/Write and refresh operations; ... - 2017 Feb 10
Design Software Engineer
Los Angeles, CA
... Ananthapur, India GPA: 3.70/4.0 B.Tech, Electronics & Communication Engineering, 2009-2013 PROGRAMMING/TECHNICAL SKILL SET: CAD tools : Cadence Virtuoso, HSPICE, MATLAB Simulink Languages : C, VHDL, Verilog HDL, SQL, PL/SQL and UNIX Scripting. ... - 2017 Feb 01
... Ananthapur, India GPA: 3.70/4.0 B.Tech, Electronics & Communication Engineering, 2009-2013 PROGRAMMING/TECHNICAL SKILL SET: CAD tools : Cadence Virtuoso, HSPICE, MATLAB Simulink Languages : C, VHDL, Verilog HDL, SQL, PL/SQL and UNIX Scripting. ... - 2017 Feb 01
Engineer Design
Canyon Country, CA, 91351
... Cadence OrCAD/Capture/Allegro/PSpice, Mentor Graphics PADS/Eldo, MPLAB-X IDE, LabVIEW, Matlab/Simulink, SQL, Minitab, Verilog-XL, Modelsim Verilog/VHDL simulator, MAX+PLUS-II, Quartus-II, ISE Foundation (Xilinx) Equipment: Working knowledge of ... - 2016 Dec 12
... Cadence OrCAD/Capture/Allegro/PSpice, Mentor Graphics PADS/Eldo, MPLAB-X IDE, LabVIEW, Matlab/Simulink, SQL, Minitab, Verilog-XL, Modelsim Verilog/VHDL simulator, MAX+PLUS-II, Quartus-II, ISE Foundation (Xilinx) Equipment: Working knowledge of ... - 2016 Dec 12
Hardware Design Engineer
Los Angeles, CA
... India Aug’14 Bachelors of Technology in Electronics and Communication Engineering GPA: 3.8/4 Technical Skills: Languages : Verilog, VHDL, System Verilog, Perl, Bash, C++, Python, Tcl, JAVA, Assembly Language (MIPS, 8086) Tools : PinSesc, Encounter, ... - 2016 Nov 14
... India Aug’14 Bachelors of Technology in Electronics and Communication Engineering GPA: 3.8/4 Technical Skills: Languages : Verilog, VHDL, System Verilog, Perl, Bash, C++, Python, Tcl, JAVA, Assembly Language (MIPS, 8086) Tools : PinSesc, Encounter, ... - 2016 Nov 14
Manager Systems Administrator
Los Angeles, CA
... Software installation (Verilog, Synopsys, video conference, CAD tool updates,etc.). UNIX System software upgrades. Bourne Shell programming. C Shell programming. UNIX System maintenance. UNIX peripheral configuration and maintenance. SOLARIS 2.51 ... - 2016 Nov 01
... Software installation (Verilog, Synopsys, video conference, CAD tool updates,etc.). UNIX System software upgrades. Bourne Shell programming. C Shell programming. UNIX System maintenance. UNIX peripheral configuration and maintenance. SOLARIS 2.51 ... - 2016 Nov 01
Embedded System and Software Engineer
La Crescenta-Montrose, CA
... League Technical Acumen Verilog VHDL FPGA ARM Microcontrollers C++ Java Printed-Circuit-Board Design Arduino Microcontrollers CNC Perl SQL PHP Microsoft Office Suite (Word, Excel) Open Office Eclipse Visual Studio PostgreSQL Linux Bash HDL - 2016 Sep 20
... League Technical Acumen Verilog VHDL FPGA ARM Microcontrollers C++ Java Printed-Circuit-Board Design Arduino Microcontrollers CNC Perl SQL PHP Microsoft Office Suite (Word, Excel) Open Office Eclipse Visual Studio PostgreSQL Linux Bash HDL - 2016 Sep 20
Electrical Engineer Engineering
Moorpark, CA, 93021
... Assisted with debugging Beta prototype product in preparation for IPO release Created internal documentation processes where none existed Validation of product hardware and Verilog HDL which controlled IGBTs, ADCs and touch screen PCBs AiTECH ... - 2016 Aug 10
... Assisted with debugging Beta prototype product in preparation for IPO release Created internal documentation processes where none existed Validation of product hardware and Verilog HDL which controlled IGBTs, ADCs and touch screen PCBs AiTECH ... - 2016 Aug 10