Design Software Engineer
Resume:
SIVA KUMAR GOVINDAN
PULLMAN,WA 99163
Mobile: (509) 592 – 1312 Email: ****************@*****.*** Summary:
Seeking an intern position in areas of Digital/Analog Circuit Design and verification ; where my experience in the fields can be utilized and adds value to the organization.
Proficient in digital/analog circuit design using TSMC 65nm and 130 nm CMOS technologies.
Performed Virtuoso layout/XL on several different analog circuits, implementing proper matching techniques.
Designed and simulated active noise reduction circuits using operational amplifiers, transistors and filters.
Hard working, Meticulous, Ability to multi-task and work in a dynamic and team oriented environment. EDUCATION:
Washington State University, Pullman, WA GPA: 3.65/4.0 MS, Electrical Engineering, 2016-Present
Research Work:
Working on 143nW Relaxation Oscillator used extensively in Ultra-low power Biomedical Systems, trying to reduce its power and flicker noise.
Course Work:
Design of Analog CMOS Integrated Circuits CMOS VLSI Design Advanced Analog Integrated Circuits RF and Microwave Circuits and Systems ASIC and Digital Systems Design Jawaharlal Nehru Technological University, Ananthapur, India GPA: 3.70/4.0 B.Tech, Electronics & Communication Engineering, 2009-2013 PROGRAMMING/TECHNICAL SKILL SET:
CAD tools : Cadence Virtuoso, HSPICE, MATLAB Simulink Languages : C, VHDL, Verilog HDL, SQL, PL/SQL and UNIX Scripting. Operating Systems : UNIX, Linux (Ubuntu) and Windows. ACADEMIC PROJECTS: AUG 2016– DEC 2016
1. Comparative performance evaluation of dynamic and static flip-flops in 65 nm technology node: WSU
Undertook performance evaluation of the following flipflops: implicit-pulsed, data-close-to-output, semi dynamic hybrid flip-flop (ip-DCO), hybrid latch-flip-flop, semi dynamic edge-triggered flip-flop, time borrowing master-slave flip-flop (tb-SMS), explicit-pulsed, hybrid static flip-flop (ep-SFF) dual edge- triggered explicit-pulsed static hybrid flop (ep-DSFF).
Submitted a detailed report in the form of an IEEE 6-page conference paper comparing the D-Q delay, minimum E*D product point, total device width and total energy of the dynamic and static flipflops. 2. Design of Single-Stage Op-amp for both NMOS and PMOS input stage in 130nm technology node: WSU
Analyzed and submitted a report that included first-pass design calculations for all bias conditions, transistor sizes, small-signal performances, schematics, bias circuits for generating any biases that are used in the circuit. Comparison between the two designs and an explanation of why a particular design should be chosen.
Simulated layout of the Single-stage Op-amp with DRC and LVS reports for both designs are carried out. 3. Design of Two-Stage Op-amp for both NMOS and PMOS input stage in 130nm technology node: WSU
Analyzed and submitted a report that included first-pass design calculations for all bias conditions, transistor sizes, small-signal performances, schematics, bias circuits for generating any biases that are used in the circuit. Comparison between the two designs and an explanation of why a particular design should be chosen. PROFESSIONAL EXPERIENCE:
Worked as Software Engineer from Nov 2013 – Aug 2016 in Tech Mahindra for client CISCO. Customer Registry was my team responsible for providing the enterprise with single source of truth for customer master data.
Involved in coding packages, procedures and functions in plsql.
Worked on production issues, P1/P2 incident calls, monthly and quarterly deployements and releases.
Worked in teams and learned how to work well with others as a team member.
Contact this candidate