Xu Zheng

Education

**/****-******* ********** ** Southern California, Los Angeles Expected Graduation: May 2017 Master in Electrical Engineering GPA: 3.87

**/****-**/**** **’an Jiaotong University, China

Bachelor in Electronic Science and Technology GPA: 88.3/100 USC Coursework

Computer Systems Organization (EE457)

VLSI System Design (Front-end, EE577A)

VLSI System Design (Post-end, EE577B)

Asynchronous VLSI Design (EE 552)

Digital System Design (EE560)

Computer Systems Architecture (EE557)

Analysis of Algorithms (CSCI570)

MOS VLSI Circuit Design (EE477)

Project Experience

DDR3 Controller Design (Verilog, NCSim, DC Compiler, Prime Time, Cadence Encounter) November 2016

Designed a DDR3 controller in Verilog RTL supporting Scalar, Block, Atomic Read/Write and refresh operations;

Realized synthesis, pre and post simulation, automatic place and route and managed setup and hold violations;

Performed static timing analysis (STA) and logic equivalence checking. DFT Labs (Verilog, NCSim, DC Compiler, TetraMax) October 2016

Created a Bidirectional Digital Timer and synthesized with inserted DFT scan cells;

Implemented IDDQ testing and Automatic Test Pattern Generation (ATPG) for path delay faults using TetraMAX;

Designed a simplified BIST architecture with LFSR and built up a fault table for testing. Multi-Terminal Maze Router Design (Verilog, Cadence NCSim) September 2016

Found the shortest path to connect multiple terminals on an 8*8 2D grid with obstacles using Lee’s Algorithm;

Verified the function in NCSim and improved the coding to realize for delay optimization. Multi-Core Multi-Thread CPU Design (VHDL, ModelSim, Xilinx ISE) July 2016

Designed a fine-grained 4-thread CMT;

Implemented Cache coherency and LL&SC for 4Core 4Threaded network processor on Artix-7 FPGA; 5-Stage General Purpose Processor Full Custom Design(Cadence Virtuoso, Perl) May 2016

Designed the schematic and implemented the layout of a 16-bit pipeline processor, including 4 16x16 SRAM banks;

Front-end Perl for instruction fetching and decoding; Back-end Perl for results verification;

Applied power and delay optimization through data gating and register rebalancing to achieve a 3.5ns clock period. Asynchronous Network on Chip (System Verilog, Proteus) April 2016

Implemented tree topology for 16 routers communication through asynchronous channels using System Verilog;

Developed test bench for function and performance test;

Synthesized in TSMC45nm asynchronous cell library using Proteus CAD Flow. 800 MHz Digital Phase Locked Loop (Cadence Virtuoso) November 2015

Designed the schematic and implemented the layout for DPLL, including Phase Frequency Detector, Charge Pump, Filter, Voltage Control Oscillator and Divider; Simulated for functional test and implemented area optimization. Research Experience

International Dielectric Research Center, Xi’an Jiaotong University; Xi’an, China December 2013-June 2015 Prepared the low-temperature co-fired molybdenum-based microwave dielectric material (LTCC). Publication

Microwave Dielectric Properties of LiKSm2(MoO4)4 Ceramics with Ultralow Sintering Temperatures, Journal of the American Ceramic Society, 2015, 98 [9] 2716-2719. DOI: 10.1111/jace.13759 Technical Skills

Programming: Verilog, System Verilog, VHDL, MATLAB, C, Perl, tcl. Tools: Cadence (Virtuoso, Encounter), NCSim, SPECTURE, Modelsim, Xilinx ISE, Chipscope Pro, Hspice, Matlab Protocols: PCI Bus, I2C, UART, AXI

Tel: 213-***-**** E-mail: acyq9n@r.postjobfree.com

Add: 2676 1/2 Ellendale Pl, Los Angeles, CA 90007

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