SHREYAA NAGPAL

**** ********* ***** #*** *** Angeles CA-90007 Phone: +213-***-**** acxhva@r.postjobfree.com https://www.linkedin.com/in/shreyaa-nagpal

Objective:

Seeking a full time/Co-op opportunity that offers a greater challenge, promotes creative thinking, encourages participation and team building to excel in my field and add value to the firm as a Computer Architecture and Digital Designer Education:

University of Southern California, Los Angeles, California May’17 Masters in Electrical Engineering GPA: 3.5/4

Course Work: Computer System Organization, Digital System Design, VLSI System Design, Network Processor Design and Programming Guru Gobind Singh Indraprastha University, India Aug’14 Bachelors of Technology in Electronics and Communication Engineering GPA: 3.8/4 Technical Skills:

Languages : Verilog, VHDL, System Verilog, Perl, Bash, C++, Python, Tcl, JAVA, Assembly Language (MIPS, 8086)

Tools : PinSesc, Encounter, PrimeTime, NCSim, Graphlab, ModelSim, Xilinx ISE, Cadence Virtuoso, CA LISA

Platforms : MacOS, Windows, NetFPGA, DeterLab, Diligent Nexys 3, Diligent Nexys 4, Unix, Linux

Additional : DDR2, DDR3, DRAM, SRAM, FIFO, CAM, LIFO, AXI, UART, PCI, I2C, GIT, SVN, Deep Neural Network

Academic Projects:

Asynchronous, Dynamic, Graph Parallel Computation (Ongoing) tools: PinSesc, GraphLab, PIN, C++

Investigating asynchronous graph processing techniques using parallel Machine Learning framework to achieve high speeds

Optimizing the performance of the cache simulator for PageRank algorithm on PinSesc tool DDR2 and DDR3 Memory Controller tools: Verilog, NCSim, Encounter, PrimeTime

Designed the DDR2 and DDR3 initialization and power up along with processing logic module for scalar, block and atomic read/write Multiple Terminal Maze Router Design tools: Verilog, NCSim, Lee’s algorithm

Implemented a multi-terminal router with SRAM using Manhattan-style connections and optimized it for shortest path trace back Design of Tomasulo Processor with MIPS ISA tools: ModelSim, VHDL, Xilinx ISE

Collaborated with a team of 3 to build a 32 bit Tomasulo Processor that supports out of order execution and in order retirement

Executed BPB (Branch Prediction Buffer), RAS (Return Address Stack), FRL (Free Register List), Dispatch Unit, Issue Unit, Store Buffer, Store Address Buffer, Load Store queue, CFC (Copy-free Checkpoints), ROB (Reorder Buffer) modules in the Tomasulo processor Multi Core Multi Thread Processor tools: NetFPGA, Verilog, Xilinx ISE

Teamed up with three to build a 64 bit 5 stage 2 core 4 threaded pipelined Network Processor using a MIPS ISA instructions

Incorporated Deep Packet Inspection algorithm to find malicious patterns incoming in the network and drop the packets

Extended the traditional BRAM Memory to a Convertible FIFO memory for interfacing between the Processor and Network Chip Multiprocessor-Chip Multithreading tools: ModelSim, Assembly Language

Implemented a 4 core and 4 threaded processor using MOOESI protocol and provided mutual exclusion using LL and SC instructions ARM’s Advanced Extensible Interconnect protocol tools: ModelSim, VHDL

Determined the routing protocol to route packets using AXI to connect 4 processors with 4 memory units in a 2X4 Mesh Topology Design of general purpose microprocessor tools: Cadence Virtuoso, Perl

Concerted effort to design a 32 bit 5 stage pipelined processor in a full custom design optimizing it for delay, power, area using clock gating, power gating, high speed D flip flops, logical effort and dynamic logic techniques

Formulated a 1024 bit SRAM (Instruction Memory and Data Memory) with 16-bit wide word having read circuitry, write circuitry and row and column decoders along with sense amplifiers and precharge circuit LIFI Technology tools: Embedded Systems

Optimized the usage of radio spectrum using data and audio transmission through visible light communication LIFI (“Light Fidelity”) Professional Experience:

Accenture Services Pvt. Ltd., India Associate Software Engineer Oct’14 – Jul’15

Handled Service Virtualization and Test Automation for Client Citi Group Project as a CA LISA Developer

Accounted for optimizing the application development lifecycle and eliminating constraints, costs and complexity from the process of delivering enterprise software

MK Infosystems Pvt. Ltd., India Summer Trainee Jun’13– Aug’13

Visited various Telecom Service Providers to understand system designing and implementation of CCTV’s and Camera Sensors Kyrion Robotics Club., India Summer Trainee Jun’12– Sep’12

Built a propeller clock and an LED Cube using Atmel 8 bit AVR RISC Microcontroller Publications:

N. Rathee, S.Nagpal, A.Malik, C. Khandelwal “An Efficient Intelligent System for Data Communication using LIFI Technology”,IJCT

N. Rathee, S.Nagpal, A. Malik “Transmission of Numeric Data and Voice Using Light Fidelity (LIFI) Technology”,IJRASET

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