| Resume alert | Resumes 31 - 40 of 117 |
Sales Support, Pricing and Contracting
The Colony, TX
... Conducted data collection, synthesis and interpretation to report accurate and actionable metrics. Served as a liaison between division stakeholders, functional teams and customer. Managed vendor and partner relations. Acquired increased ... - 2017 Nov 08
... Conducted data collection, synthesis and interpretation to report accurate and actionable metrics. Served as a liaison between division stakeholders, functional teams and customer. Managed vendor and partner relations. Acquired increased ... - 2017 Nov 08
Design Electrical Engineering
Richardson, TX
... Performing the logic synthesis to generate a gate-level netlist with an operating frequency of less than 30MHz. Implementation of chip of area less than 0.4mm2. DRC, RC extraction, CTS, SI, Flip Chip Planning are analyzed. Design of Differential ... - 2017 Sep 01
... Performing the logic synthesis to generate a gate-level netlist with an operating frequency of less than 30MHz. Implementation of chip of area less than 0.4mm2. DRC, RC extraction, CTS, SI, Flip Chip Planning are analyzed. Design of Differential ... - 2017 Sep 01
Design Electrical Engineering
Richardson, TX
... ASIC DSP chip – RTL design, Physical design and Synthesis • A. Specification development and architecture design for semi-custom programmable audio processor ASIC chip. It involved RTL design, logic simulation, gate level synthesis, schematic & ... - 2017 Aug 19
... ASIC DSP chip – RTL design, Physical design and Synthesis • A. Specification development and architecture design for semi-custom programmable audio processor ASIC chip. It involved RTL design, logic simulation, gate level synthesis, schematic & ... - 2017 Aug 19
Design Electrical Engineer
Arlington, TX
... Experienced in CMOS VLSI design, Verilog RTL coding, Simulation, Synthesis, Map and Place & Route, Layout (LVS). Experienced in ASIC front end/back end design, Physical Design flow, SOC Level Verification in System Verilog and C. Hands on experience ... - 2017 Jun 15
... Experienced in CMOS VLSI design, Verilog RTL coding, Simulation, Synthesis, Map and Place & Route, Layout (LVS). Experienced in ASIC front end/back end design, Physical Design flow, SOC Level Verification in System Verilog and C. Hands on experience ... - 2017 Jun 15
Japanese/English Bilingual Translator/Interpreter
Plano, TX
... 1 (porous Metal Organic Polyhedra) crystals in laboratory Studies and utilized X-ray diffraction crystallography to verify synthesis of MOP-1 crystals Learned how to create a research poster using Microsoft Powerpoint Created and presented research ... - 2017 Apr 10
... 1 (porous Metal Organic Polyhedra) crystals in laboratory Studies and utilized X-ray diffraction crystallography to verify synthesis of MOP-1 crystals Learned how to create a research poster using Microsoft Powerpoint Created and presented research ... - 2017 Apr 10
Engineer Process
Bedford, TX
... Working knowledge of both life and physical science techniques and processes Work History Madico Inc / Lintec of America NSTC, RICHARDSON, Texas Process Engineer Oct 06, 2014 - May 11, 2016 Synthesis of vertically aligned carbon nanotube arrays in ... - 2017 Mar 21
... Working knowledge of both life and physical science techniques and processes Work History Madico Inc / Lintec of America NSTC, RICHARDSON, Texas Process Engineer Oct 06, 2014 - May 11, 2016 Synthesis of vertically aligned carbon nanotube arrays in ... - 2017 Mar 21
Electrical Engineering
Frisco, TX
... 2014 Learned FPGA and ASIC Design methodologies and synthesis coding styles Designed RTL modules and verified by writing testbenches in Verilog HDL on Adders, Flip-flops, ALU, Multiplexers, Decoders, Dual Ram, FIFO, RAM_256, Shift Registers and FSM. ... - 2017 Mar 02
... 2014 Learned FPGA and ASIC Design methodologies and synthesis coding styles Designed RTL modules and verified by writing testbenches in Verilog HDL on Adders, Flip-flops, ALU, Multiplexers, Decoders, Dual Ram, FIFO, RAM_256, Shift Registers and FSM. ... - 2017 Mar 02
Biomedical Engineer
Irving, TX
... Technical Skills Lab skill: - Biological Evaluation Techniques: Liquid Chromatography, Dialysis, Cell Culture Assays, Bacterial Culture, Western Blotting, SDS-PAGE, ELISA, Protein Synthesis and Purification, Immunohistochemistry, Protein ... - 2017 Jan 18
... Technical Skills Lab skill: - Biological Evaluation Techniques: Liquid Chromatography, Dialysis, Cell Culture Assays, Bacterial Culture, Western Blotting, SDS-PAGE, ELISA, Protein Synthesis and Purification, Immunohistochemistry, Protein ... - 2017 Jan 18
Engineering Assistant
Arlington, TX
... processes, cleaning room working experience, failure analysis, magnetic optical and electrical properties characterization, electrochemical process, development of metallic nanostructures and sensors, thin films synthesis and characterization. ... - 2016 Oct 16
... processes, cleaning room working experience, failure analysis, magnetic optical and electrical properties characterization, electrochemical process, development of metallic nanostructures and sensors, thin films synthesis and characterization. ... - 2016 Oct 16
Manager Project
Grand Prairie, TX
... Other transversal competences: high analysis and synthesis capacity, methodical, assertive, leader, results oriented. Some highlighted achievements are: Implementation of European standard quality systems and control of production efficiency in the ... - 2016 Oct 10
... Other transversal competences: high analysis and synthesis capacity, methodical, assertive, leader, results oriented. Some highlighted achievements are: Implementation of European standard quality systems and control of production efficiency in the ... - 2016 Oct 10