Design Electrical Engineering
Resume:
VIJAY KOUSHIK BELAGUR SUDEESH
**** ******** ****, **** ***, Dallas, Texas - 75252
972-***-**** *****.**********@*****.*** https://in.linkedin.com/in/vijaykoushik OBJECTIVE: MS EE Graduate skilled in RTL design, Physical design, EDA and scripting seeking entry level opportunities In Digital VLSI. (ASIC, FPGA, Computer architecture or Machine learning). EDUCATION:
Master of Science in Electrical Engineering
The University of Texas at Dallas, Richardson, Texas August 2015 – May 2017
GPA: 3.87 / 4.0
Bachelor of Engineering in Electronics and Communications Engineering Bangalore Institute of Technology, Bangalore, India June 2011 – May 2015
Percentage: 81.56%
TECHNICAL SKILLS:
Programming languages: C, Verilog, VHDL, Perl, Python, Tcl, shell scripting. Software tools : Matlab, LabVIEW, Xilinx (ISE, Vivado), Modelsim, Tetramax (for ATPG), GNU compiler, HSpice. Physical design tools : Cadence (Specter, Virtuoso, Assura, Encounter); Synopsys (Design vision, SiliconSmart, Primetime, IC Compiler). Miscellaneous : PCB design (Diptrace), Linux, GIT, Makefile, lab tools (Oscilloscope, Network Analyzer, Function generator). RELEVANT COURSEWORK:
Physical Design Automation Computer Architecture Analog Computing ASIC Design Analog IC Design FPGAs and Reconfigurable Systems Testing and Testable design (DFT, BIST) Wireless Communication Lab VLSI Design ACADEMIC PROJECTS:
Machine learning and data analytics in semiconductor fabrication (January 2017 – May 2017 )
• Designed a Genetic algorithm based feature selection algorithm for building a regression model using MARS to reduce test cost of analog and RF chips. The model achieved 98% accuracy on industrial data of 12000 ICs compacting tests by 28%.
• Scan cell insertion; and test pattern generation to determine test vectors, and identifying stuck at faults and fault coverage. Reconfigurable Systems – FPGA Softcore (September 2016 – December 2016)
• Analysis and study of an analog accelerator with FPGA to achieve low power, high-performance analog computing model.
• Design and implementation of a customizable overlay microprocessor on FPGA with keyboard and VGA interface. ASIC DSP chip – RTL design, Physical design and Synthesis
• A. Specification development and architecture design for semi-custom programmable audio processor ASIC chip. It involved RTL design, logic simulation, gate level synthesis, schematic & layout design (DRC &LVS), placement & routing using IC Compiler
• B. Created Standard cell library to Implement the physical design of ALU and performed functional verification and STA. Beacons – MIPS based architecture design for establishing physical network (March 2016 – May 2016)
• Verilog implementation of MIPS-based pipelined architecture to perform low-level computation on the chip and coordinate high-level computation and data sharing in a cloud, in a physical network established with BLE and Wi-Fi based beacons. Analog IC Design – Two-stage amplifier (March 2016 – May 2016)
• Designed a differential input; single-ended output Two-Stage amplifier in 0.35- m CMOS. The bias currents were generated by the self-biased bandgap current source and current mirrors. It included a start-up circuit in the self-biased current source. Wireless communication, Laboratory experience (August 2015 – December 2015)
• Developed code for performing frame synchronization, channel estimation and equalization using Matlab and LabVIEW. Simulated baseband digital modem for various modulation schemes on a software defined radio and implemented a Wi-Fi sniffer. Simulated annealing based algorithm for partition and placement (September 2015 – November 2015)
• A. Implemented a parser and data structure in C for bi-partitioning of netlists to obtain minimum cut size on IBM benchmarks.
• B. Implemented a fixed die standard cell placer engine based on Timberwolf method to minimize total wire length on the chip. Industrial automation using IOT (December 2014 – March 2015)
• Designed an ARM-based system to enable inter-device communication and data sharing. It executed tasks autonomously or with minimal user interaction by monitoring data and comparing it with previously recorded values in the database. ACTIVITIES:
Mini projects using embedded hardware
• Programmed microcontrollers (Raspberry Pi, Arduino, atmega) to operate and interface sensors and peripheral devices.
• Built simple autonomous robots. Implemented basic home automation system and health monitoring system. Member - Rotaract club, Bangalore
• Tutored high school students in basic science. Organized Health camps and coordinated a Sports and Cultural fest. WORK EXPERIENCE:
Graduate research assistant, Micronex (MEMS) Lab – UT Dallas (March 2016 – May 2017)
• Design, fabrication (Lithography, etching, deposition) of MEMS devices like piezo resistors, resonators, accelerometers etc.
• Worked on electrostatic MEMS motors. Built PCBs to test and analyze the performance of MEMS devices. Work Authorization & availability: F1 Student Visa (EAD) JUNE 2017 Hello,
I am Vijay Koushik. I recently completed my Master's in Electrical Engineering (VLSI circuits and systems) from University of Texas at Dallas. I am seeking entry level opportunities in the area of Digital VLSI or computer architecture. My specialization is in VLSI design with my coursework involving ASIC design, FPGA systems, Computer architecture, MEMS and Machine learning.
I have sound knowledge in RTL design, logic simulation, spice simulation, physical design and synthesis P&R, STA along with necessary CAD tools and scripting in LINUX environment. I have structured my coursework and research to involve certain tangential domains like and wireless communication and MEMS sensor architecture and design, involving fabrication and lab tools. Further, my current coursework involves study and design of machine learning based test methods and data analytics for efficient low-cost testing of RF and analog IC chips. The idea is to leverage software to reduce dependence on the high cost and time consuming requirement of ATE.
My projects that are related to this domain are:
1. ASIC design of DSP chip for a programmable audio processor. 2. MIPS based architecture design for distributed computing in physical network and data sharing. 3. Customizable general purpose microprocessor soft-core on FPGA. I am greatly interested in interdisciplinary aspects that could be centered around Circuits and systems leveraging their advantages together to come up with exciting alternatives. I volunteered as a research assistant in a couple of research labs at the university. I worked towards survey articles and projects related to bio-design automation, overlay architecture and Network-on-chip(NoC) for FPGA systems, 3D IC design, and analog computing. I feel I have the right skillset and would be a great fit. I have worked on the toolsets and concepts that were mentioned in requirements, as part of my academic research and projects. I just wanted to reiterate my strong interest as it's related to VLSI design and Computer architecture, matching closely to my specialization. I have attached my resume with all the relevant details. Please let me know if I need to provide any other information. Thank you for your time.
Regards
Vijay koushik
*****.**********@*****.***
https://www.linkedin.com/in/vijaykoushik
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