Professional Summary

Motivated Electrical design engineer with over 2 years’ experience in engineering design and implementation which include VLSI design (Digital and Analog IC), functional/logic design, verification test and implementation. Looking for a challenging position in the field of low power design and system level design.

Knowledge and Experience

Strong educational background in Integrated Circuit design, Digital logic implementation and Low power design.

Professional experience and strong academic knowledge in Verification, Validation and Testing of chip design.

Experienced in CMOS VLSI design, Verilog RTL coding, Simulation, Synthesis, Map and Place & Route, Layout (LVS).

Experienced in ASIC front end/back end design, Physical Design flow, SOC Level Verification in System Verilog and C.

Hands on experience in System Verilog methodologies like UVM,OVM and System architectures x64, x86 and ARM.

Strong skill set in VHDL, Verilog, Cadence tools, RTL design, simulation and synthesis using Xilinx ISE, XST tools.

Education

Texas, TX University of Texas at Arlington Expected May 2017

Masters in Electrical Engineering GPA: 3.3/4 Course work: Digital VLSI Design, Silicon IC fabrication techniques, Microprocessor Systems, Analog CMOS IC Design, Digital Signal Processing, Mixed CMOS IC Design, Data Communications

India, AP KL University CGPA: 3.85/4

Bachelors in Electronics and Communication Engineering Aug 2010 – May 2014

Course work: Digital Logic Design, VLSI CAD, Advanced Digital IC Design, Embedded Software, CPLD and FPGA Architecture

Work Experience

Jr Electrical Engineer Semcon Technologies June 2014 – May 2015

Designed RTL modules in Verilog HDL to develop algorithms in MATLAB, and verified them by writing test benches.

Performed analysis of circuit performance, evaluation of test results and developed project based design solutions.

Student Researcher KL University Dec 2012 – April 2014

Collaborated and led a team of 6 students with research focused on Cadence 180nm technology for ultra-low power applications for 18months.

Played key role in designing "Low Power CMOS Analog multiplexer" that resulted in meeting the requirement of both ultra-low power and voltage applications of 0.4 Volts.

Exhibited initiative and desire to learn new aspects. Took on new responsibilities as a student mentor for research.

Project Experience

Verification of MIPS Processor using System Verilog Aug 2016 – Dec 2016

Developed System Verilog based test bench with Driver, Receiver, Virtual Interface and Scoreboard.

Verified the design with test bench wrote in System Verilog including manual-set tests, random tests, code coverage and function coverage.

Design of a Re-configurable Data Converter (RDC) Jan 2016 – May 2016

Made a system level design for 5kHz switch frequency, 8-bit DAC. Chose a power supply voltage of 1V. Chose the MOSFET sizes. Determined the proposed DAC specifications using the ideal DAC.

Designed a programmable data converter cell (PDCC), the basic block of design which can be configured as a switch, ADC/DAC. Tuned the circuits simulated transient response, signal gain at AC analysis and frequency plot.

Verified using Cadence Virtuoso. Achieved high gain of 59.8dB, CMRR of 84dB, Unity gain bandwidth of 54.4MHz.

Design of low power CMOS Analog multiplexer Aug 2014 – May 2015

Designed a high speed 8-channel analog multiplexer in 180nm technology. Chose ultra-low operating voltage of 0.4V

Implemented the concept of modified transmission gate using dynamic threshold (DTMOS) and achieved nearly 20% less power and voltage consumption.

Utilized Cadence suits to design and simulate the schematics of each component within the multiplexer.

Skills

Tools & Languages: C, C++, MATLAB, Simulink, Perl, PLC programming, Python, Lab View, Multi-Sim, P-spice, H-spice

Methodologies: UVM, OVM

Protocols: CAN bus, Ethernet

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