Design Electrical Engineering
Resume:
Manisha Koneru
LinkedIn: https://www.linkedin.com/in/mkoneru E-Mail: *********@********.*** Cell: 469-***-****
OBJECTIVE
Seeking a challenging position in Electrical Engineering, as Design Engineer, to share, explore and enrich my knowledge to face the challenges utilizing excellent problem solving with strong determination and hard work.
EDUCATION
Masters in Electrical & Electronics Engineering – Circuits & Systems GPA: 3.222 of 4
University of Texas at Dallas, Richardson, TX. May 2017
Bachelor of Technology - Electronics and Communication Engineering GPA: 9.02 of 10
V R Siddhartha Engineering College (Autonomous), JNTUK, AP, India. 2015
COMPUTER SKILLS
Languages : Verilog/VHDL, C, Core JAVA, Perl, Python, System Verilog.
Hardware : FPGA Kits – Spartan-3E and Virtex-6 Boards, Microcontroller 8086.
Hardware Tools : Cadence, Synopsys, Encounter, Siliconsmart & Tetramax, Mentor Graphics, MATLAB, Simulink, ModelSim, UVM, Lab View, Multisim, Xilinx, HSpice, System Generator.
COURSE WORK
ASIC Design Testing and Testable Design Digital Signal Processing Hardware Modelling using HDL
VLSI Design Advanced Digital Logic Energy Harvesting, Storage and Powering for Microsystems, PMIC’s
RFIC Design Computer Architecture Analog Integrated Circuit Design Active Semiconductor Devices
ACADEMIC PROJECTS
Design of Low Noise Amplifier
A cascode circuit with a common source amplifier with inductive degeneration and a common gate amplifier.
The common source is to achieve a high gain, the common gate buffer is to achieve good isolation between ports.
Design of Low Dropout Regulator
Dropout voltage, low quiescent current, transient Voltage Tolerance are the key performance indicators of LDO.
Pole-Zero cancellation through ESR of load capacitor, insertion of voltage buffer for better Impedance matching.
Inserting a zero with phase lead compensation using very low quiescent current and achieves good phase margin.
Design of Mini Stereo Digital Audio Processor
Implementation of the Architecture in Verilog, verifying its functionality with the C/MATLAB Codes.
Verilog gate-level netlist and Behavioral codes are compiled and simulated by Mentor Graphic ModelSim.
Performing the logic synthesis to generate a gate-level netlist with an operating frequency of less than 30MHz.
Implementation of chip of area less than 0.4mm2. DRC, RC extraction, CTS, SI, Flip Chip Planning are analyzed.
Design of Differential input Single-ended output Two-Stage Operational Amplifier using 0.35-µm CMOS Technology
It is a stable amplifier with a phase margin of 600, differential gain of 90dB and power dissipation of 0.25mW.
The bias currents were generated by self-biased current source with a start-up circuit and current mirrors.
Two-pole Amplifier, a differential amplifier followed by a common source amplifier was designed.
Design and Implementation of Single Precision Floating Point Multiplier using CAD Tools
Simulation & Synthesis of the Verilog Code in the Synopsys Toolset resulting of about 2500 cells.
Design and Layout of logic gates and Library Characterization of those gates using Siliconsmart.
Performing Automatic Place Route to layout the chip, Primetime Analysis and analyzing the Power and Delay.
FPGA Implementation of Efficient Vedic FFT Processor for its application in OFDM Systems
It is implemented on Virtex-6 ML605 Evaluation Board with the aid of Chip Scope Analyser, System Generator.
Design of Double Precision Floating Point Multiplier, ROM, 24-bit Vedic Multiplier, Controller (32-bit VIO).
Design Verification - BIST & SCAN, DFT, Fault Analysis, Test Pattern Generation
Design of Multipliers, Shift registers and FSM’s, performing ATPG, implementing the BIST&SCAN Architectures.
Performing High level Synthesis by Linear programming, Optimization by Graph Theory and Fault Analysis.
Implementation of Low Power VLSI Circuits in Mentor Graphics using Energy Efficient Adiabatic Logic
Design of logic gates by reducing the switching activity, capacitance and Power consumption in CMOS digital IC’s.
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