Sign in

Design Data

Houston, TX
$80 on corp to corp
January 09, 2020

Contact this candidate



***** **** ******* *****, **** Tree, CO-80124 (USA)




14+ years of experience in requirements gathering, analysis, definition, recommendation, system architecture, detailed design, development, testing, support, documentation and maintenance of Electronics instruments

12+ years of experience in digital designs using Xilinx ISE design flow for synthesis, simulation and implementation on Xilinx FPGAs

6+ months experience with Xilinx Vivado design Suite for High Level Synthesis for Xilinx SoCs (ZynQ)

Good understanding of other hardware description languages e.g. Verilog, System Verilog for design and simulation

Ability to develop test benches and verify HDL code/netlist for functional and timing simulation

Knowledge of FPGA architectures and other on-chip components (soft and hard IPs) to architect custom designs for specific processing requirements

Understanding of design constraints for guiding synthesis and P&R CAD tools to develop high performance RTL designs

Participated in complete design & development cycle of customized scientific instruments from user specific requirement analysis/concept, architecture, design to final product testing & delivery

Experience of circuit design, analysis, and PCB layout design (up to 6 layers)

Design experience with standard digital control and data communication interfaces and protocols (USB 2.0, SPI, I2C, RS232)

Proficient in troubleshooting and debugging of hardware designs to quickly identify and isolate faulty components/modules

Experience with data analysis, algorithm, Test GUI development for scientific applications

Ability to quickly learn new skills and apply them for successful project execution

Experience using lab equipments e.g. high-speed oscilloscopes, pulse generators, logic analyzers, spectrum analyzers etc.

Good understanding of computer architecture, programming languages, IDE (e.g. Visual Studio) for windows based software development

Good understanding of object-oriented development using C#

Excellent people skills to collaborate in a multi-disciplinary, cross-cultural and dynamic team environment


M. Tech. (Microelectronics, VLSI & Display Technology), 9.5/10, 2005, Indian Institute of Technology (IIT) Kanpur, India

B. Tech. (Electronics & Communication Engineering), 7.9/10, 2002, Kurukshetra University, India


Technical Consultant, JDTPL Bangalore; 2015 -till date

Scientific Officer C/D/E, DAE India; 2005- 2015

DGFS Trainee, IIT Kanpur; 2003-2005


Certified Scrum Master (Scrum Alliance) – to be completed soon


EDA Tools: Xilinx ISE (9.2, 12.3), Mentor Graphics Modelsim XE (12.3), Keil µVision (3.0), Cadence Orcad (14.0), Protel, Altera’s Quartus II 4.2, Xilinx Vivado Design Suite – HLx (2018.1)

FPGA based Logic Designs: FPGAs (Xilinx Spartan Series), VHDL, CDC (Clock Domain Crossing), STA (Static Timing Analysis), High Level Synthesis using C, Verification & Validation Methology, UVM

Software Development: NI Labwindows, Visual Studio, Measurement Studio

Embedded Systems: 8051 based Microcontrollers, Embedded C/C++, Keil uVision, Bare metal programming, RTOS


1FPGA based Modular Instruments for Scientific Applications (2015 - 2020):

Instruments based on modular architecture are required for various experimental studies in a lab setup. Modular architecture supports integration of in-house modules to build customized instruments at low cost. This is particularly suitable for redesigning legacy instruments using advanced technology and devices, while meeting changing design requirements due to obsolescence.


Develop complete understanding of design specification of commercially available instruments/products as per the client’s requirements

Develop system architecture for a complete experimental set-up with integrated test and measurement instrument system

Do market survey to select commercial off-the-shelf instruments/components for technical comparison and cost analysis

Prioritize the design tasks and convert them into multiple design sub-tasks for implementation using available modules

Initiate design and development of new hardware and components using contracted facilities

Participate in in-house design reviews, technical meetings and documentation

Complete RTL design and embedded firmware development for FPGA based design tasks

Work with verification and validation team to generate testcases and debug FPGA based designs

Develop flow diagrams, algorithms and interface protocols for interfacing FPGA to other onboard components (e.g. microcontroller, FIFOs, A/D and D/A Converters, SRAM etc.)

Supervise work of other group members doing schematic entry, component placement and layout of board level designs

Contribute to test plans and procedures for multi-level testing of design boards using PC based test utilities

Analysis of test data for functional and performance evaluation before final testing/delivery

Development of application specific data analysis algorithms for its integration with application software

Finalize user interface design for PC based instruments and develop software requirement specification documents

Work with third party for software development and monitor its progress

Demonstration of working boards with fully functional FPGA software, embedded firmware and PC based application software to clients

2Design and development of Pulse Arrival Time Recorder, BARC Mumbai (2013 - 2015):

This is an FPGA based Single Input Pulse Arrival Time Recorder and it can record arrival time of each input pulse with a time resolution of 5ns. Start of the data acquisition can be synchronized with an external trigger or a user command from PC. Time stamping and data acquisition continues for user selectable pre-fixed time period. A STOP button on front panel can terminate this process prematurely. An onboard microcontroller acts as an interface between FPGA and PC. It decodes commands, sends status signals and transfers time stamp of each input pulse to PC through USB interface.


Developed an architecture for FPGA implementation of core functionality

Completed detailed RTL design of core, VHDL coding, simulation and synthesis

Integrated VHDL coded time stamping core module with existing interfaces for other onboard components i.e. microcontroller, FIFOs and other I/Os

Developed firmware to generate status and control signals for PC based data acquisition and control using USB 2.0

Developed PC based test GUI to control start/stop, to acquire data and to display test data using graphs

Tested Time Stamp Recorder using available FPGA based test set-up consisting of test board, a general-purpose FPGA module and standard lab instruments

3Design & Development of FPGA based DAQ Module with USB interface, BARC Mumbai (2011-2013):

This is a multi-mode FPGA based data acquisition module for time stamping and counting applications. The design architecture of DAQ module is chosen to accommodate common processing functions of these applications. It incorporates an advanced FPGA (Xilinx Spartan-6, XC6SLX9), high capacity dual FIFOs and high-performance microcontroller (Cypress CY7C68013A) with USB interface on a single board. A complete instrument design integrates DAQ module with additional custom circuitry as per the specific requirements.


Proposed modular design approach to support iterative and adaptive hardware development

Developed architecture of DAQ module and converted it into detailed schematic design

Finalized design of test-board with additional onboard components to test design based on DAQ module

Developed reusable interfaces for FPGA implementation for onboard microcontroller, FIFOs and other I/Os

Prepared detailed documents for internal approval of development work for DAQ module

Supervised development progress of DAQ module and completed acceptance testing of fabricated boards using developed test interfaces and test board

Developed firmware (ANSI C) for CY7C68013A to control data transfer using USB2.0 interface

4Design & development of MCS for spatial distribution profiling, BARC Mumbai (2010 - 2013):

An MCS records count rate of events with respect of time. The time-axis of MCS is mapped to rotation of a drum and each rotation is synchronized using trigger signals from drum-controller. The core functionality of MCS is implemented on FPGA and onboard SRAM stores intermediate counts. This design is different from standard design with respect to synchronization of external trigger with start/stop of multichannel scaling.


Identified alternate application of MCS; actively participated in requirement gathering of end user experimental setup, finalization of specifications and preparation of System Requirement Specification document

Detailed RTL design using VHDL, simulation and synthesis for Xilinx FPGA (Spartan 2)

Develop detailed test plan for basic, functional and performance testing of MCS

Developed firmware to generate status and control signals for PC based data acquisition and control

Developed detailed documents for interfacing with software development group

Components procurement, co-ordination with assembly group and complete testing using developed PC based Graphical User Interface for RS232

Lab demonstration, field trials and publication in departmental symposium in NSNI-2013

Detailed technical documentation e.g. SyRS, detailed design, test procedures and instruction manual

5Design of FPGA based Ratio to Digital Converter (RDC), BARC Mumbai (2009-2011):

Ratio to Digital Converters are integral part of readout electronics of position sensitive detectors in neutron diffraction spectrometers. The ratio of the two signals from a position sensitive detector, gives information about position of the interaction of x-rays within the detector. It is used to construct diffraction pattern to study sample structures.


Analyzed schematic designs of existing RDC modules and RDC controller to understand complete experimental setup

Proposed an FPGA based integrated design with onboard shaping amplifiers

Identified digital processing functions to be implemented on FPGA and developed conversion algorithm

Co-operated with other team members to prepare detailed design and layout plan

6Design & development of MCS with standard features, BARC Mumbai (2008 - 2009):

A Multi-Channel Scalar records count rate over time. The core functionality of MCS is implemented on FPGA and onboard FIFOs store intermediate counts.


Finalized specifications and features to be implemented e.g. bin width, scan length and behavior with respect to external trigger

Completed schematic entry, BOM and PCB layout (4 layers) of complete MCS design with FPGA, Microcontroller, FIFOs, comparators along with other components using Orcad tools

Developed detailed test plan for basic, functional and performance testing of MCS

Developed architecture for FPGA implementation of MCS core functionality

Detailed RTL design using VHDL, simulation and synthesis for Xilinx FPGA (Spartan 2)

Developed firmware to generate status and control signals for PC based data acquisition and control

Developed detailed documents for interfacing with software development group

Components procurement, co-ordination with assembly group and complete testing using developed PC based Graphical User Interface for RS232

Lab demonstration and publication in departmental symposium, NSNI-2010

Detailed technical documentation e.g. SyRS, detailed design, test procedures etc.

7Design & development of Low Noise Front End ASIC for SDD, BARC Mumbai (2006-2007):

The ASIC has been designed and developed in 0.7 um CMOS technology. It is a low noise analog pulse-processing channel designed especially for Silicon Drift Detector. It consists of charge sensitive amplifier (CSA), two amplifier stages followed by two low pass Sallen key filter stages.


Detailed study of existing readout electronics for Silicon Drift Detectors

Studied techniques for noise reduction for shaping amplifiers and CMOS preamplifiers

Did extensive simulations to find the optimum shaping time constant

Completed design of charge sensitive preamplifier using adaptive bias for PMOS transistor operating in sub-threshold region

Worked with layout design team to complete backend design using IC station (DRC check, LVS, IC extract) to generate GDSII for tape-out

8Microcontroller based VME bus Emulator, IGCAR Kalpakkam (2006):

This is a micro controller (AT89C51ED2) based VME bus card to test other VME cards of computer-based control and instrumentation systems.


Analyzed specifications and functionality of existing VME I/O cards to prepare detailed specifications

Developed architecture, detailed design and flow diagrams for testing each card I/O

Prepared detailed technical document for approval and interfacing with other groups

9Design & development of FPGA based VME bus Interface Controller, IIT Kanpur & IGCAR Kalpakkam (2004-2005):

This is a FPGA based full custom design that acts as an interface between onboard Motorola CPU 68020 and VME bus backplane interface. Design was targeted for implementation on Altera MAX7000S series CPLD.


Identified functions to be implemented for FPGA based custom design

Developed architecture, detailed RTL design, and VHDL coding

Developed test-benches to verify design at module and top level

Simulation, synthesis and implementation

Contact this candidate