UJJWAL KAUSHIK

882-***-****

Email: acrz65@r.postjobfree.com

Career Objective

To work enthusiastically in a semiconductor industry which would help me follow my passion in VLSI domain and help to get the best out of me and prove myself as an important asset to the company.

Summary

Good Understanding of the ASIC and FPGA Design Flow.

Extensive experience in writing RTL Models in Verilog HDL with all coding styles and flat and layered Testbenches in System Verilog.

Expertise in verification methodologies like UVM, OVM.

Experience in using Industry Standard EDA Tools for the front-end design and verification.

Knowledge of STA.

Hands on scripting languages like Perl, Python.

Strong analytical capabilities and capable to work with broader team. Highlights/Skills

Verilog SystemVerilog

VHDL Assertions based verification

RTL coding Verification Methodologies(UVM, OVM)

Directed test flat/layered testbenches

Perl Python

FPGA CMOS fabrication

ASIC design SOC verification

Functional Coverage Verification plan

Code debugging UART,SPI, AMBA protocols

Educational qualification

10th standard

Maharaja Agarsain Public School

81.6% (2009)

12th standard

Govt. Boys Sr. Secondary school

80.6% in major (2011)

B.tech (Electronics and communication)

KIIT college of Engineering

73.8%(2011-2015)

PG Diploma (VLSI design and verification)

March, 2015 – July, 2015

VLSI Projects

[1] Router 1x3 – RTL design and Verification

HDL: Verilog

HVL: SystemVerilog

TB Methodology: UVM

EDA Tools: Questasim and ISE

Responsibilities:

Architected the design

Implemented RTL using Verilog HDL.

Architected the class based verification environment using system Verilog

Verified the RTL model using SystemVerilog.

Generated functional and code coverage for the RTL verification sign-off

Synthesized the design

[2] SPI Controller Core - Verification

HVL: System Verilog

TB Methodology: UVM

EDA Tools: Questasim

Responsibilities:

Architected the class based verification environment in UVM

Verified the RTL module using System Verilog

Generated functional and code coverage for the RTL verification sign-off

[3] UART- IP Core – Verification

HVL : System Verilog

TB Methodology: UVM

EDA Tools: Questasim

Responsibilities:

Architected the class based verification environment in UVM

Verified the RTL module using System Verilog

Generated functional and code coverage for the RTL verification sign-off Technical Skill

Skill set Specific Proficiency

OS Windows, Linux Professional

EDA Tool Xilinx’s ISE, Project

Navigator, QuestaSim,

ModelSim

Professional

Programming language C/C++ Intermediate

Verilog-HDL Professional

VHDL Intermediate

MATLAB Intermediate

Perl Professional

Python Professional

College Level Projects

Project 1: Mobile charger using dynamo attached to a bicycle in 3rd Semester.

Project 2: Mechanical robotic arm in 4th Semester.

Project 3: Mobile jammer in 5th Semester.

Project 4: RFID based automatic door opener and theft control system in 6th Semester.

Project 5:

a) RED OBJECT DETECTION in live video stream in 7th Semester. b) VIRTUAL MOUSE CONTROL using hand/finger gesture in 7th Semester. c) Yet to implement “6TH SENSE TECHNOLOGY” inspired by Pranav Mistry.

Project 6: Mini Router 1X3 design using Verilog RTL code and verification in 8th Semester.

Technical Achievements

1st place in “CIRCUIT PUZZLE COMPETITION” in 2013.

1st place in “ELECTRONICS PROJECT” of exhibition in 2014.

1st place in “BEST PROJECT IDEA TECHFEST-2014”.

Participated in “TEXAS INSTRUMENTS ANALOG DESIGN CONTEST

(INDIA) 2015”.

Participated in “SYNPOSIS VLSI DESIGNING COMPETITION”. Assembly Intermediate

Other Technical

Softwares

Edwin XP Intermediate

KEIL 8051 Intermediate

Tinapro Intermediate

Pspice Intermediate

Application Software Ms Office, Photoshop Hands on Hobbies

Playing guitar.

Playing volleyball and table tennis.

Listening to music.

Clay molding.

Teaching.

Reading and talking about new emerging technologies. Personal Details

Father’s Name Mr. Sunil Kumar Kaushik

Date of Birth June 19th, 1993

Gender Male

Nationality Indian

Marital status Unmarried

Languages Known Hindi, English

Permanent address H.no 557/1 Pana Udhyan Mohalla dangri Walan Narela, Delhi -110040, India

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