Sathish K. Kumar
214-***-**** firstname.lastname@example.org https://www.linkedin.com/in/sathishkkumar
“Education is the passport to the future, for tomorrow belongs to those who prepare for it today.”
- Malcolm X
To obtain an internship/full-time position in the field of Analog and Mixed Signal IC design. EDUCATION
Master of Science in Electrical Engineering (MSEE), The University of Texas at Dallas; From January 2017, CGPA – 3.6/4 (till date).
RF IC Design, Data Converters, Power Management Circuits, Advanced VLSI Design, Analog Integrated Circuit Design, VLSI Design, Design and Analysis of Reconfigurable Systems, Advanced Digital Logic, Computer Architecture, Active Semiconductor Devices.
Bachelor of Engineering, Anna University, Chennai, India (Electrical and Electronics Engineering); August 2008 to April 2012, CGPA- 8.24/10
Tools - Xilinx ISE, SDK, Vivado HLS, ModelSim, Cadence - Spectre, Virtuoso, DRC, LVS, PEX
- Synopsis - Scirocco, HSPICE, DesignVision, Primetime, Tetramax, Waveview HDL : Verilog, System Verilog
Hardware : Zybo Zync-7000 ARM/FPGA
Others : Python, Perl, TCL, C, C++, Java, SQL, Salesforce Projects : LNA, LDO, DAC, ADC, Amplifier, SRAM, ASIC, FPGA Certifications and Training:
• System Verilog for Design and Verification 20.3 – Cadence (In progress)
• Oracle Certified Web Services Developer, Oracle Certified Professional, Java SE 6 Programmer
• Salesforce.com Certified Developer (Dev401)
Organization: TATA Consultancy Services Limited, Chennai, India June 2012 – Dec 2016 Designation: IT Analyst
Client Handled: The Home Depot Inc.
Development of mobile application for tablet and mobile devices and supporting and enhancing the desktop, mobile, and cloud-based applications. Engaging and working with coordination across the technical teams, end users, vendors and teams across various regions and location. Received “Outstanding Performance award – Gem of TCS” 3 years in a row during 2014, 2015 and 2016. GRADUATE ACADEMIC PROJECTS
Title: Design and development of Vivado IP for k-NN algorithm (Fall’17) Custom IP for computing k-NN algorithm has been designed and developed using Vivado HLS and Vivado Block design. This design is implemented on Zybo Zynq-7000 and tested using Xilinx SDK. Title: Design of LDO (Fall’17)
Low power 180mA LDO has been designed using 350nm technology. Design and simulation were done in Cadence tools.
Title: Design and layout of 256 words SRAM. (Summer’17) Designed and drawn custom layout of 256 words (8 bits) SRAM in 65nm technology library provided by Global Foundries. Calibre Engine for DRC, LVS and PEX and Synopsis tools for timing and waveform analysis is used. Title: IC design and layout of Radix-2 butterfly structure for FFT algorithm. (Spring’17) Designed and drawn the layout of standard cells (130nm technology) and used Auto-Place-and-Route to complete the final layout. Used Cadence, Synopsis, ModelSim and Xilinx tools in this project. Title: Design of First-order Delta-Sigma ADC for Glucometer. (Spring’17) Designed 2-stage differential op-amp and other components required for First Order Delta-Sigma ADC for low power and low voltage medical instrumentation. All the circuit simulations are done using Cadence tool (350nm technology).
Title: Cache Design and Branch Predictor performance analysis of CPU. (Spring’17) Designed and analyzed CPU performance with different Cache and Branch predictors. The design is optimized for cost-effective and performance efficiency with different benchmarks using Gem5 simulator.